Iterative remapping respecting timing constraints

Abstract

This paper proposes a novel iterative remapping approach for area reduction while still respecting the timing constraints of the design specification. The use of complex gates can potentially reduce cell area, but they have to be chosen wisely to preserve timing constraints while remapping. Commercial tools for logic synthesis work better with simple cells and are not fully capable of taking advantage of complex cells; the strategy proposed herein is aimed to better exploit complex cells during technology mapping. The proposed iterative remapping approach can exploit a larger amount of logic gates, reducing global circuit area and respecting global timing constraints. Experiments show area improvement of 8% on average and up to 15% for a subset of combinational mapped circuits of IWLS 2005 benchmarks.