Ground gated 8T SRAM cells with enhanced read and hold data stability

A new asymmetrically ground-gated eight-transistor (8T) static random access memory (SRAM) circuit with enhanced data stability characteristics is proposed in this paper. A robust and low leakage SLEEP mode with data retention capability is provided by utilizing asymmetrical ground gating in an idle memory array. The data stability is enhanced by 2.22× and 53.54% during read operations and data retention SLEEP mode, respectively, with the proposed asymmetrically ground-gated 8T memory circuit as compared to a conventional ground-gated six-transistor (6T) SRAM cell in a TSMC 65nm CMOS technology. The overall electrical quality is also enhanced by 2.84× with the proposed asymmetrically ground-gated 8T SRAM circuit as compared to the conventional ground-gated 6T memory array.