{"title":"Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow","authors":"Matheus T. Moreira, Ney Laert Vilar Calazans","doi":"10.1109/ISVLSI.2013.6654647","DOIUrl":null,"url":null,"abstract":"This work presents the ASCEnD flow, a design flow devised for the design of components required for the design of asynchronous systems using standard-cells. The flow is fully automated except for the layout generation step, and can be parameterized for any CMOS technology. It was employed in the design of a dedicated standard-cell library, which contains over five hundred components, for the STMicroelectronics 65 nm technology. This library supported implementation of different circuits, like network-on-chip routers and cryptographic cores.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2013.6654647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This work presents the ASCEnD flow, a design flow devised for the design of components required for the design of asynchronous systems using standard-cells. The flow is fully automated except for the layout generation step, and can be parameterized for any CMOS technology. It was employed in the design of a dedicated standard-cell library, which contains over five hundred components, for the STMicroelectronics 65 nm technology. This library supported implementation of different circuits, like network-on-chip routers and cryptographic cores.