2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

{"title":"Symbolic verification of timed asynchronous hardware protocols","authors":"Krishnaji Desai, K. Stevens, J. O'Leary","doi":"10.1109/ISVLSI.2013.6654650","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654650","url":null,"abstract":"Correct interaction of asynchronous protocols requires verification. Timed asynchronous protocols add another layer of complexity to the verification challenge. A methodology and automated tool flow have been developed for verifying systems of timed asynchronous circuits through compositional model checking of formal models with symbolic methods. The approach uses relative timing constraints to model timing in asynchronous hardware protocols - a novel mapping of timing into the verification flow. Relative timing constraints are enforced at the interface external to the protocol component. SAT based and BDD based methods are explored employing both interleaving and simultaneous compositions. We present our representation of relative timing constraints, its mapping to a formal model, and results obtained using NuSMV on several moderate sized asynchronous protocol examples. The results show that the capability of previous methods is enhanced to enable the hierarchical verification of substantially larger timed systems.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123251807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins","authors":"K. Sarfraz, V. Kursun","doi":"10.1109/ISVLSI.2013.6654624","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654624","url":null,"abstract":"A seven transistor (7T) static random-access memory (SRAM) cell with single-ended read and write operations is evaluated in this paper. The cell topology consists of a single bitline, a cross-coupled inverter pair with a transmission gate employed in the feedback path, and a bitline access transistor. Simulation results with 8 Kib SRAM arrays indicate up to 49.3% reduction in leakage currents, 42.7% shorter read delay, 36.9% lower write delay, and 75.4% wider voltage margin during write operations with the 7T SRAM cells while providing similar read static noise margin (RSNM) characteristics as compared to the conventional six transistor (6T) SRAM cells in TSMC 65nm standard CMOS technology. These performance benefits are achieved at the cost of 63.0% larger cell area, 70.6% higher read power consumption, and 57.9% higher write power consumption as compared to the conventional 6T SRAM cells.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133859963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Murphy goes 3D","authors":"E. Marinissen","doi":"10.1109/ISVLSI.2013.6654641","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654641","url":null,"abstract":"“Whatever can, will go wrong” is the famous quote attributed to Edward Murphy. It has given Murphy the status of patron saint of all test engineers, since it is Murphy's Law that keeps them in business. Three-dimensional stacking of ICs have kept the communities in both technology and design research busy for several years now. No wonder, because 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all these benefits can only materialize if 3D-SICs can be properly tested for manufacturing defects. Only recently, the test community has started to work on test solutions for these IC products, signaling that their high-volume market introduction is now imminent. This talk gives an overview of 3D-SIC technologies, associated test challenges, and emerging solutions.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131908203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel method to mitigate TSV electromigration for 3D ICs","authors":"Yuanqing Cheng, A. Todri, A. Bosio, Luigi Dillio, P. Girard, A. Virazel, P. Vivet, M. Belleville","doi":"10.1109/ISVLSI.2013.6654633","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654633","url":null,"abstract":"Three-dimensional (3D) integration is considered to be a promising technology to tackle the global interconnect scaling problem for tera-scale integrated circuits (ICs). 3D ICs typically employ through-silicon-vias (TSVs) to connect planar circuits vertically. Due to its immature fabrication process, several defects such as void, misalignment and dust contamination, may be introduced. These defects can increase current densities within TSVs significantly and cause severe electromigration (EM) effect, which can degrade the reliability of 3D ICs considerably. In this paper, we propose a novel method to mitigate EM effect of the defective TSV. At first, we analyze various possible TSV defects and demonstrate that they can aggravate electromigration dramatically. Based on the observation that EM effect can be alleviated significantly by balancing the direction of current flow within TSV, we design an on-line self-healing circuit to protect defective TSVs, which can be detected during test procedure, from EM without degrading performance. Experimental results show that our proposed method can achieve tens times improvement on mean time to failure (MTTF) compared to the design without using such method with negligible hardware overheads and power consumption.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116424070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Routing-aware resource allocation for mixture preparation in digital microfluidic biochips","authors":"Sudip Roy, P. Chakrabarti, Srijan Kumar, B. Bhattacharya, K. Chakrabarty","doi":"10.1109/ISVLSI.2013.6654653","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654653","url":null,"abstract":"On-chip mixing of several biochemical fluids with a specified ratio of concentration factors is a challenging problem in automating biochemical laboratory protocols on a digital microfluidic biochip. The performance of a mixing algorithm depends on resource allocation, e.g., the placement of mixer modules, storage units, boundary reservoirs or dispensers on the chip floor. With a limited number of resources, mixing of a large number of fluids may be slowed down because of the stalls arising out of fluidic constraints during droplet transportation. In this paper, we propose a routing-aware resource allocation technique which can be adopted with two basic mixing algorithms. Simulation results show that on an average, the proposed scheme can reduce the number of droplet crossing paths by 75.4% or by 89.7%, depending on the underlying basic algorithm used for mixture preparation.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122648246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"STAIRoute: Global routing using monotone staircase channels","authors":"B. Kar, S. Sur-Kolay, C. Mandal","doi":"10.1109/ISVLSI.2013.6654628","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654628","url":null,"abstract":"This work proposes a new algorithm for global routing using monotone staircase channels obtained from VLSI floorplan topology. Unlike the existing global routers that follow block placement stage, it immediately follows the floorplanning stage of VLSI design. The monotone staircase channels are identified using the results of recent O(nk log n) top-down hierarchical monotone staircase bipartition. The worst case time complexity of the proposed global routing algorithm is O(n2kt), where n, k and t denote the number of blocks, nets and the number of terminals in a given net respectively for a given floorplan. Experimental results on the MCNC/GSRC floorplanning benchmark circuits show that our method obtained 100% routability for each of the nets, without any over-congestion through the monotone staircase channels. The wire length for each of the t-terminal (t ≥ 2) nets is comparable to the steiner length of that net in almost all cases.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130632760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications","authors":"L. Józwiak","doi":"10.1109/ISVLSI.2013.6654612","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654612","url":null,"abstract":"Summary form only given. The recent spectacular progress in modern nano-dimension semiconductor technology enabled implementation of a very complex multi-processor system on a single chip (MPSoC), mobile and autonomous computing, global networking and wire-less communication, and facilitated a fast progress in these areas. New important opportunities have been created. The traditional applications can be served much better and numerous new sorts of embedded systems became technologically feasible and economically justified. Various monitoring, control, communication or multi-media systems that can be put on or embedded in (mobile, poorly accessible or distant) objects, installations, machines or devices, or even implanted in human or animal body can serve as examples. However, many of the modern embedded application impose very stringent functional and parametric demands. Moreover, the spectacular advances in microelectronics introduced unusual silicon and system complexity. The combination of the huge complexity with the stringent application requirements results in numerous serious design and development challenges, such as: accounting in design for more aspects and related complex multi-objective MPSoC optimization, adequate resolution of numerous complex design tradeoffs, reduction of the design productivity gap for the increasingly complex and sophisticated systems, reduction of the time-to market and development costs without compromising the system quality, etc. These challenges cannot be well addressed without an adequate system and design methodology adaptation. The first part of the presentation is devoted to discussion of the serious issues and challenges in development of contemporary and future demanding embedded systems and introduction of the quality-driven model-based design methodology proposed by the presenter. Subsequently, the Intel's ASIP-based MPSoC technology is introduced, and a new automatic design flow for heterogeneous ASIP- based MPSoCs is discussed, when focusing on the system and processor level design- space exploration (DSE) involving coherent HW/SW architecture co-synthesis, macro- and micro-architecture design tradeoff exploitation, and application-specific memory and communication design. This flow and its EDA tools are results from the European research project ASAM (Automatic Architecture Synthesis and Application Mapping for MPSoCs based on adaptable ASIPs) performed in the framework of the industrial research program ARTEMIS. The final presentation part overviews several methods and EDA-tools of the ASAM flow focusing on the micro-architecture level DSE involving the application analysis and parallelization, ASIP micro-architecture synthesis and application scheduling and mapping, combined in one coherent HW/SW co-synthesis process.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123911413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Saliency-driven dynamic configuration of HMAX for energy-efficient multi-object recognition","authors":"Sungho Park, Ahmed Al-Maashri, Yang Xiao, K. Irick, N. Vijaykrishnan","doi":"10.1109/ISVLSI.2013.6654636","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654636","url":null,"abstract":"Object recognition is one of the most important tasks in computer vision due to its wide variety of applications from small hand-held devices to surveillance systems in large public facilities. Even though biologically inspired approaches have been recently revealed to take another significant step forward to reduce its large power consumption, it still consumes relatively large amounts of energy because of the immense amount of data and computations. Typically in such biologically inspired - often called neuromorphic - object recognition implementations, visual saliency feeds feature extraction to limit the amount of computations effectively by picking a pre-determined size of patches around salient locations of an image. In this work, we explore the design space of HMAX for neuromorphic feature-extraction and classification along with the trade-off between energy consumption and classification accuracy. In addition, a novel method to further reduce energy consumption is proposed by leveraging effort-level of HMAX according to the findings of visual saliency in an efficient manner. Experiments revealed that our dynamic configuration achieved 70.57% of energy reduction with only 1.05% of accuracy loss for accuracy-critical applications. For energy-critical applications, a proposed configurations trades off 5.07% accuracy to gain 91.72% reduction in energy consumption.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115914955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Do we need wide flits in Networks-on-Chip?","authors":"Junghee Lee, C. Nicopoulos, S. Park, M. Swaminathan, Jongman Kim","doi":"10.1109/ISVLSI.2013.6654614","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654614","url":null,"abstract":"Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose microprocessors adopt a certain flit width without any reasoning or explanation. In fact, it is not easy to pinpoint an optimal flit size, because the flit size is intricately intertwined with various aspects of the system. This paper aims to provide a guideline on how to choose an appropriate flit width. It will be demonstrated that arbitrarily choosing a flit width without proper investigation may have serious repercussions on the overall behavior of the system.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On runtime task graph extraction in MPSoC","authors":"Kunal P. Ganeshpure, S. Kundu","doi":"10.1109/ISVLSI.2013.6654654","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654654","url":null,"abstract":"In a Multi Processor System on Chip (MPSoC), an application executes on multiple processor cores connected by a Network on Chip (NoC). An application is represented in the form of a Task Graph consisting of nodes and edges which correspond to operations (tasks) and communication between these nodes, respectively. The task graph is scheduled on an MPSoC platform by generating a task to core assignment so as to minimize the total execution time. Static scheduling of a task graph is optimized based on estimated execution times on the MPSoC hardware platforms. Dynamic scheduling is challenging because the task graph must be available during runtime while making scheduling decisions. However, dynamic scheduling offers the benefits of portability and adaptability. Runtime discovery of task graph is one of the main challenges faced by dynamic scheduling due to unavailability of application task graph. In this work, we present a novel mechanism for runtime task graph extraction based on the observation that an application goes through several phases during its execution. During a stable phase, the same task graph (Phase Graph) repeatedly executes for a very large number of iterations. Experimental results show that task graphs can be extracted within as few as 200 iterations during a program phase.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127379116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}