{"title":"Murphy goes 3D","authors":"E. Marinissen","doi":"10.1109/ISVLSI.2013.6654641","DOIUrl":null,"url":null,"abstract":"“Whatever can, will go wrong” is the famous quote attributed to Edward Murphy. It has given Murphy the status of patron saint of all test engineers, since it is Murphy's Law that keeps them in business. Three-dimensional stacking of ICs have kept the communities in both technology and design research busy for several years now. No wonder, because 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all these benefits can only materialize if 3D-SICs can be properly tested for manufacturing defects. Only recently, the test community has started to work on test solutions for these IC products, signaling that their high-volume market introduction is now imminent. This talk gives an overview of 3D-SIC technologies, associated test challenges, and emerging solutions.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2013.6654641","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
“Whatever can, will go wrong” is the famous quote attributed to Edward Murphy. It has given Murphy the status of patron saint of all test engineers, since it is Murphy's Law that keeps them in business. Three-dimensional stacking of ICs have kept the communities in both technology and design research busy for several years now. No wonder, because 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all these benefits can only materialize if 3D-SICs can be properly tested for manufacturing defects. Only recently, the test community has started to work on test solutions for these IC products, signaling that their high-volume market introduction is now imminent. This talk gives an overview of 3D-SIC technologies, associated test challenges, and emerging solutions.