STAIRoute: Global routing using monotone staircase channels

Abstract

This work proposes a new algorithm for global routing using monotone staircase channels obtained from VLSI floorplan topology. Unlike the existing global routers that follow block placement stage, it immediately follows the floorplanning stage of VLSI design. The monotone staircase channels are identified using the results of recent O(nk log n) top-down hierarchical monotone staircase bipartition. The worst case time complexity of the proposed global routing algorithm is O(n2kt), where n, k and t denote the number of blocks, nets and the number of terminals in a given net respectively for a given floorplan. Experimental results on the MCNC/GSRC floorplanning benchmark circuits show that our method obtained 100% routability for each of the nets, without any over-congestion through the monotone staircase channels. The wire length for each of the t-terminal (t ≥ 2) nets is comparable to the steiner length of that net in almost all cases.