2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第3页

High and low side high voltage switch with over voltage and over current protection 高、低侧高压开关，具有过压、过流保护

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654655

W. L. Terçariol, R. Sáez, I. Nascimento

引用次数: 3

NAND Flash memory: The driving technology in digital storage - Overview and challenges NAND快闪记忆体:数位储存的驱动技术-概述与挑战

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654640

M. d'Abreu

{"title":"NAND Flash memory: The driving technology in digital storage - Overview and challenges","authors":"M. d'Abreu","doi":"10.1109/ISVLSI.2013.6654640","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654640","url":null,"abstract":"Summary form only given. Nand Flash memory is the NVM technology of choice for solid storage devices. This talk will give an introduction to Flash Non Volatile Memory (NVM). For completeness the talk will also present Nor Flash as well as the roles for Nand and Nor Flash. The second part of the talk will be focused on issues related to reliability and endurance, and current solutions and future challenges. Despite the advantages, NAND-based storage systems are not without challenges. For the next decade, Flash storage systems are expected to provide solutions with reduced product costs, further improved read/write performance at low power consumption, as well as better data integrity for the users. Growth in storage demand is phenomenal, which leads to the adoption of more aggressive technology to keep cost reasonable. This further leads to using smaller cells (~10nm in geometry), as well as more bits/cell to improve storage density, as well as cost. Newer physical storage media requires closer system-level interaction to make the system feasible for reliable data storage solution. State-of-the-art error correcting coding (ECC) solution, as well as advanced memory signal processing (MSP) techniques, will be deployed to make future flash media reliable for all data storage customers. In addition, new system solutions will provide the NAND-based storage system longer endurance and better data retention. The talk will conclude with a discussion of challenges that require significant research.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"47-48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Data extraction from SystemC designs using debug symbols and the SystemC API 使用调试符号和SystemC API从SystemC设计中提取数据

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654618

Jannis Stoppe, R. Wille, R. Drechsler

{"title":"Data extraction from SystemC designs using debug symbols and the SystemC API","authors":"Jannis Stoppe, R. Wille, R. Drechsler","doi":"10.1109/ISVLSI.2013.6654618","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654618","url":null,"abstract":"Due to the ever increasing complexity of hardware and hardware/software co-designs, developers strive for higher levels of abstractions in the early stages of the design flow. To address these demands, design at the Electronic System Level (ESL) has been introduced. SystemC currently is the “defacto standard” for ESL design. The extraction of data from system designs written in SystemC is thereby crucial e.g. for the proper understanding of a given system. However, no satisfactory support of reflection/introspection of SystemC has been provided yet. Previously proposed methods for this purpose either focus on static aspects only, restrict the language means of SystemC, or rely on modifications of the compiler and/or parser. In this work, we present an approach that overcomes these limitations. A methodology is introduced which enables full extraction of the desired information from a given SystemC design without changing the SystemC library or the compiler. For this purpose, debug symbols generated by the compiler and SystemC API calls are exploited. The proposed system retrieves both, static and dynamic information. A comparison to previously proposed solutions shows the benefits of the proposed method, while its application is illustrated by means of a visualization engine.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127856932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores 性能和节能缓存系统设计:在异构核心上同时执行多个应用程序

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654659

N. Venkateswaran, Kartik Lakshminarasimhan, A. Sridhar, P. Thinakaran, R. Hariharan, V. Srinivasan, R. Kannan, Aswinkumar Sridharan

{"title":"Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores","authors":"N. Venkateswaran, Kartik Lakshminarasimhan, A. Sridhar, P. Thinakaran, R. Hariharan, V. Srinivasan, R. Kannan, Aswinkumar Sridharan","doi":"10.1109/ISVLSI.2013.6654659","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654659","url":null,"abstract":"Future generation supercomputing clusters are endeavouring to achieve exascale performance without compromise on energy efficiency. Executing multiple applications simultaneously without space time sharing in a heterogeneous multi core environment brings out the utmost parallelism that exists within the applications. This helps to attain peak performance and also paves way for improved resource utilization. This necessitates the need for an efficient and locality aware cache replacement scheme to cater to the magnanimous data needs of underlying functional units in case of a cache miss. Reduced cache miss improves resource utilization and reduces data movement across the core which in turn contributes to a high performance to power ratio. This paper proposes a novel application aware cache replacement policy in which data blocks are assigned weights based on a set of application and data statuses. Our proposed heuristics have shown an 8-11% improvement in cache hit when compared against conventional cache replacement heuristics.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134404541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Real-time low-power task mapping in Networks-on-Chip 片上网络中的实时低功耗任务映射

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654616

M. Norazizi, Sham Mohd Sayuti, Leandro Soares Indrusiak

引用次数: 44

Using electromagnetic emanations for variability characterization in Flash-based FPGAs 在基于flash的fpga中使用电磁辐射进行可变性表征

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-05 DOI: 10.1109/ISVLSI.2013.6654631

J. Tarrillo, Jorge Tonfat, F. Kastensmidt, R. Reis, Florent Bruguier, M. Bourree, P. Benoit, L. Torres

引用次数: 2

Fault recovery communication protocol for NoC-based MPSoCs 基于noc的mpsoc故障恢复通信协议

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654648

E. Wächter, Alexandre M. Amory, F. Moraes

引用次数: 2

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context 一种可重构多标准asip的turbo解码器，用于多asip环境下的高效动态重构

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654620

Vianney Lapôtre, Purushotham Murugappa, G. Gogniat, A. Baghdadi, J. Diguet, Jean-Noel Bazin, M. Hübner

{"title":"A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context","authors":"Vianney Lapôtre, Purushotham Murugappa, G. Gogniat, A. Baghdadi, J. Diguet, Jean-Noel Bazin, M. Hübner","doi":"10.1109/ISVLSI.2013.6654620","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654620","url":null,"abstract":"The emergence of many wireless standards is introducing the need of flexible multi-standard baseband receivers. To address this issue and to face the increasing demand of higher throughput for new greedy applications on mobile devices recent works propose multi-ASIP platforms for decoding algorithms. Furthermore dynamic evolution of communication parameters combined with the reduction of latency between two data frames imposes the need for an efficient reconfiguration management of such systems. In this context, we propose to tackle reconfiguration optimizations of a multi-standard and multi-mode ASIP for turbo decoding in order to improve the global reconfiguration management of a multi-ASIP platform. A comprehensive analysis concerning the area impact and dynamic reconfiguration performance is presented. Proposed ASIP configuration optimizations lead to a low area overhead of 0.004 mm2 in 65 nm CMOS technology. For a multi-ASIP platform in which 8 ASIPs are implemented on a same device the configuration load is divided by ten thanks to both ASIP optimizations and an efficient configuration infrastructure.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130695112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Determining the test sources/sinks for NoC TAMs 确定NoC tam的测试源/接收器

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654615

Alexandre M. Amory, E. I. Moreno, F. Moraes, M. Lubaszewski

引用次数: 0

Program phase duration prediction and its application to fine-grain power management 程序相位持续时间预测及其在细粒度电源管理中的应用

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654634

S. Srinivasan, Raghavan Kumar, S. Kundu

{"title":"Program phase duration prediction and its application to fine-grain power management","authors":"S. Srinivasan, Raghavan Kumar, S. Kundu","doi":"10.1109/ISVLSI.2013.6654634","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654634","url":null,"abstract":"To achieve energy optimal computing, processor resources must be adjusted dynamically to the computing needs of a program. The computational needs of an application may change during its execution depending on the type and locality of the processed data. It has been previously suggested that while a processor waits for data on a cache miss, dynamic voltage and frequency scaling (DVFS) may be used to reduce the energy consumption. However, due to the overheads involved in DVFS such as capacitor charging/discharging time and PLL locking time, fine-grain DVFS did not gain attraction. In this paper, we present a fine-grain DVFS scheme based on the prediction of program execution behavior. If a program is predicted to stay in a low IPC mode for a long period, it may be worthwhile to tolerate the PLL lock time overhead for achieving potential energy savings. The run-time prediction scheme is based on a hardware based dynamic program phase classification and next phase duration estimation. The phase duration prediction scheme is based on a linear weighted least square estimation (WLSE) approach, which is fast and incurs very low hardware overhead. Based on the simulation of several memory intensive SPEC2000 benchmarks, we show that energy reduction of > 7% can be achieved from fine-grain DVFS scheme over the traditional DVFS approach.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122670365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10