N. Venkateswaran, Kartik Lakshminarasimhan, A. Sridhar, P. Thinakaran, R. Hariharan, V. Srinivasan, R. Kannan, Aswinkumar Sridharan
{"title":"性能和节能缓存系统设计:在异构核心上同时执行多个应用程序","authors":"N. Venkateswaran, Kartik Lakshminarasimhan, A. Sridhar, P. Thinakaran, R. Hariharan, V. Srinivasan, R. Kannan, Aswinkumar Sridharan","doi":"10.1109/ISVLSI.2013.6654659","DOIUrl":null,"url":null,"abstract":"Future generation supercomputing clusters are endeavouring to achieve exascale performance without compromise on energy efficiency. Executing multiple applications simultaneously without space time sharing in a heterogeneous multi core environment brings out the utmost parallelism that exists within the applications. This helps to attain peak performance and also paves way for improved resource utilization. This necessitates the need for an efficient and locality aware cache replacement scheme to cater to the magnanimous data needs of underlying functional units in case of a cache miss. Reduced cache miss improves resource utilization and reduces data movement across the core which in turn contributes to a high performance to power ratio. This paper proposes a novel application aware cache replacement policy in which data blocks are assigned weights based on a set of application and data statuses. Our proposed heuristics have shown an 8-11% improvement in cache hit when compared against conventional cache replacement heuristics.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores\",\"authors\":\"N. Venkateswaran, Kartik Lakshminarasimhan, A. Sridhar, P. Thinakaran, R. Hariharan, V. Srinivasan, R. Kannan, Aswinkumar Sridharan\",\"doi\":\"10.1109/ISVLSI.2013.6654659\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Future generation supercomputing clusters are endeavouring to achieve exascale performance without compromise on energy efficiency. Executing multiple applications simultaneously without space time sharing in a heterogeneous multi core environment brings out the utmost parallelism that exists within the applications. This helps to attain peak performance and also paves way for improved resource utilization. This necessitates the need for an efficient and locality aware cache replacement scheme to cater to the magnanimous data needs of underlying functional units in case of a cache miss. Reduced cache miss improves resource utilization and reduces data movement across the core which in turn contributes to a high performance to power ratio. This paper proposes a novel application aware cache replacement policy in which data blocks are assigned weights based on a set of application and data statuses. Our proposed heuristics have shown an 8-11% improvement in cache hit when compared against conventional cache replacement heuristics.\",\"PeriodicalId\":439122,\"journal\":{\"name\":\"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"volume\":\"144 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2013.6654659\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2013.6654659","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores
Future generation supercomputing clusters are endeavouring to achieve exascale performance without compromise on energy efficiency. Executing multiple applications simultaneously without space time sharing in a heterogeneous multi core environment brings out the utmost parallelism that exists within the applications. This helps to attain peak performance and also paves way for improved resource utilization. This necessitates the need for an efficient and locality aware cache replacement scheme to cater to the magnanimous data needs of underlying functional units in case of a cache miss. Reduced cache miss improves resource utilization and reduces data movement across the core which in turn contributes to a high performance to power ratio. This paper proposes a novel application aware cache replacement policy in which data blocks are assigned weights based on a set of application and data statuses. Our proposed heuristics have shown an 8-11% improvement in cache hit when compared against conventional cache replacement heuristics.