Breaking power delivery walls using voltage stacking

Abstract

The power delivery walls include: power density (power consumption density increases beyond the heat dissipation capabilities of the technology), power and ground power delivery pins (chip power consumption requires increasing numbers of pins), 3DIC power density (physical stacking in the third dimension exacerbates the two dimensional explosion), on-chip power regulation efficiency (relatively poor efficiencies achievable with on-chip regulators limit the effectiveness of many low power schemes). This talk shows how voltage stacking is a comprehensive method for addressing the power delivery walls above, with special emphasis on 3DIC.