Memory subsystem architecture design for multimedia applications

Abstract

Multimedia applications for processing high resolution video, data and audio sequences are known to require a high speed and high density memory port. Several hardware modules accessing the same main memory simultaneously generate concurrent accesses and memory conflicts, which reduce the memory port bandwidth and increase data latency. This paper proposes to integrate the SoC modules using an intelligent memory controller, in a memory-centric design approach. Also, it presents a memory system design analysis for a multimedia SoC with an analytical model for latency reduction in a multi-level memory hierarchy.