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A new RNS to mixed-radix number converter using modulo (2/sup p/ - 1) signed-digit arithmetic 一种基于模(2/sup p/ - 1)符号数算法的RNS -混合基数转换器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412774
Shugang Wei, K. Shimizu
{"title":"A new RNS to mixed-radix number converter using modulo (2/sup p/ - 1) signed-digit arithmetic","authors":"Shugang Wei, K. Shimizu","doi":"10.1109/APCCAS.2004.1412774","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412774","url":null,"abstract":"In this paper, a hardware algorithm converting the numbers in a residue number system (RNS) to that in a mixed-radix number system by using signed-digit (SD) arithmetic is presented. In each residue digit of the RNS, integers mi = (2Pi - 1) are used as the moduli and the modulo m addition and multiplication can be performed by an end-around-carry SD adder and a binary modulo m SD adder tree, respectively. Thus a high speed converter can be designed by using the proposed modulo m SD adders and multipliers","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of LO leakage due to LO mismatch in CMOS Gilbert mixer for direct conversion application 直接转换用CMOS吉尔伯特混频器中LO失配引起的LO泄漏分析
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412753
J.J. Liu, M. Do, J. Ma, K. Yeo
{"title":"Analysis of LO leakage due to LO mismatch in CMOS Gilbert mixer for direct conversion application","authors":"J.J. Liu, M. Do, J. Ma, K. Yeo","doi":"10.1109/APCCAS.2004.1412753","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412753","url":null,"abstract":"The DC offset caused by the LO-RF feedthrough in the mixer of a direct conversion receiver is a serious problem. The LO leakage caused by the LO mismatch in double-balanced CMOS Gilbert mixers is examine and analyzed in four cases, no LO mismatch, LO phase mismatch only, LO amplitude mismatch only and the combination of the two mismatches. The relation between the mismatch and the LO leakage is derived. Simulation results shown are consistent with the analysis","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129662586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Control unit implementation for a reduced complexity reconfigurable data acquisition architecture 用于降低复杂性的可重构数据采集体系结构的控制单元实现
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413037
H. Le, A. Zayegh, J. Singh
{"title":"Control unit implementation for a reduced complexity reconfigurable data acquisition architecture","authors":"H. Le, A. Zayegh, J. Singh","doi":"10.1109/APCCAS.2004.1413037","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413037","url":null,"abstract":"A control unit for a reconfigurable data acquisition (DAQ) architecture has been presented. The reconfigurable DAQ system is employed in a digital relay for power system distance protection. It can detect and adjust its sampling speed depending on the occurrence of a fault in the network. Results indicate that a 98% reduction of average data throughput is achieved. 87% reduction of power consumption is obtained and the total sampled data is reduced by 98% when the reconfigurable algorithm is applied. This significantly reduces the system need for data storage, and hence correspondingly reduces the system complexity, and also enables an increase of the system detection speed and accuracy.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128506551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new OTA design methodology based on feedback control systems theory 基于反馈控制系统理论的OTA设计新方法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413035
L. de Carvalho Ferreira, T. Pimenta
{"title":"A new OTA design methodology based on feedback control systems theory","authors":"L. de Carvalho Ferreira, T. Pimenta","doi":"10.1109/APCCAS.2004.1413035","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413035","url":null,"abstract":"This work describes a new approach to design OTA amplifiers, based on the feedback control systems theory and on the response of a LTI system to a unit step. Thus, it is possible to specify the signal transient from the definition of overshoot and settling time. Consequently, from the proposed approach it can be verified that phase margin, unit gain frequency, DC gain and slew rate are functions of the natural oscillating frequency and the damping coefficient. They restrict the design, given that it is not possible to obtain all values independently, since only two factors determine the other four values.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123710502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
La code construction and performance analysis for LAS-2000 La -2000规范构建及性能分析
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412998
Chen-Yan Lai, H. Chu, S. Liao, Chung-Min Huang
{"title":"La code construction and performance analysis for LAS-2000","authors":"Chen-Yan Lai, H. Chu, S. Liao, Chung-Min Huang","doi":"10.1109/APCCAS.2004.1412998","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412998","url":null,"abstract":"China Wireless Telecommunications Standards Organization presented LAS-CDMA to the international standards organization 3GPP2 as a proposal from China in March of 2000. In March of.2003 Li provided views on the potential of the LAS-CDMA technology applied to a high spectral efficiency system for a 4G system. .LAS-CDMA is characterized by a multiple access scheme, based on two families of CDMA codes, LA codes and LS codes. (17, 136, 2559) LA code group is used in LAS-2000, which is physical layer modes compatible with cdma2000 for the same chip rate, carrier spacing, frame length, core network architecture and protocols. In this paper, having investigated (17, 136, 2559) LA code construction, a method of triangular array formations of correlation value distribution positions for this code group is proposed in an effort to have a further theory analysis of LA codes.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123721005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance trade-offs in designing a dual-band CMOS IEEE 802.11A/B frontend 设计双频CMOS IEEE 802.11A/B前端的性能权衡
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412762
K. Phansathitwong, H. Sjoland
{"title":"Performance trade-offs in designing a dual-band CMOS IEEE 802.11A/B frontend","authors":"K. Phansathitwong, H. Sjoland","doi":"10.1109/APCCAS.2004.1412762","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412762","url":null,"abstract":"This paper describes trade-offs involved in designing a dual-band CMOS frontend for wireless local-area network (WLAN). Three 0.18mum CMOS frontends have been investigated, a single-band frontend at the 2.4 GHz ISM band, a single-band frontend at the 5 GHz U-NII band and a dual-band frontend. The study shows that employing a dual-band frontend yields satisfactory results, although some compromises regarding the performance in the lower frequency band have to be made","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123724229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel 基于三模MAP/VA内核的统一卷积/turbo解码器架构设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413069
Fan-Min Li, P. Shen, A. Wu
{"title":"Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel","authors":"Fan-Min Li, P. Shen, A. Wu","doi":"10.1109/APCCAS.2004.1413069","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413069","url":null,"abstract":"We proposed triple-mode MAP/VA timing charts that can run two different algorithms at the same time by complementing each other. Then, we address the implementation of a reconfigurable architecture for unified convolutional/turbo decoder design. According to the triple-mode MAP/VA timing chart and by merging some similar modules in both the Viterbi decoder and the log-MAP turbo code decoder, we build one unified component decoder with both of these two functions. Besides, in order to conform to the advance communication standard, our decoder can also perform as a reconfigurable trellis decoder. That is, our design meets the requirement of the multi generator polynomial in the convolutional code specification.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130610072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Realization of multiphase sinusoidal oscillator using CDBAs 利用cdba实现多相正弦振荡器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412980
K. Klahan, W. Tangsrirat, W. Surakampontorn
{"title":"Realization of multiphase sinusoidal oscillator using CDBAs","authors":"K. Klahan, W. Tangsrirat, W. Surakampontorn","doi":"10.1109/APCCAS.2004.1412980","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412980","url":null,"abstract":"A multiphase sinusoidal oscillator with the employment of current differencing buffered amplifiers (CDBAs) as an active element is presented in this paper. The proposed oscillator circuit is composed of n cascaded lossy integrators and n inverters, which can generate 2n different phase sinusoidal voltage (180°/n and 180\"/n+180°). The oscillation frequency can be wide range adjusted, approximately 3 decades, through the value of active elements. Experimental results obtained using the AD844 ICs are given to confirm the theoretical analysis.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130790925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Complexity-aware design of a DA-based FIR filters 基于数据的FIR滤波器的复杂性感知设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412792
Chih-Chao Chen, Tay-Jyi Lin, Chih-Wei Liu, C. Jen
{"title":"Complexity-aware design of a DA-based FIR filters","authors":"Chih-Chao Chen, Tay-Jyi Lin, Chih-Wei Liu, C. Jen","doi":"10.1109/APCCAS.2004.1412792","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412792","url":null,"abstract":"This paper presents a novel technique to reduce the area of the hardwired lookup table (LUT) of DA-based FIR filters. It explores the optimal quantization on the real-valued LUT with optimal global scaling and error distribution, and we apply an effective error measure to estimate the quantization error on the FIR coefficients. Our approach enables designers to explicitly trade the quality for simple implementations at finer granularity than that solely by reducing the coefficient wordlengths. Moreover, in our simulations, the proposed method can save 30%-40% silicon area of conventional DA-based FIR filters under identical error constraints","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132268562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new LC-tank voltage controlled oscillator 一种新型LC-tank电压控制振荡器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412786
Shao-Hua Li, S. Jang, Y. Chuang, Chien-Feng Li
{"title":"A new LC-tank voltage controlled oscillator","authors":"Shao-Hua Li, S. Jang, Y. Chuang, Chien-Feng Li","doi":"10.1109/APCCAS.2004.1412786","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412786","url":null,"abstract":"This paper describes the design of a new monolithic VCO with a single nMOSFET and a single pMOSFET core. The monolithic VCO is designed in standard 0.35mum single-poly, 4-metal CMOS process. The LC tank consists of an inductor and a varactor. The requisite tuning range is obtained by using an nMOS inversion-mode varactor. The oscillator is tunable from 2.26987 to 2.64276 GHz through a MOS varactor input. Tuning range of 16.7% covers the frequency for 2.4 GHz ISM band","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128782429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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