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The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.最新文献

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A novel low noise design method for CMOS L-degeneration cascoded LNA 一种新的CMOS l -退化级联LNA低噪声设计方法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412747
Sung-Huang Lee, Y. Juang, Chin-Fong Chiu, H. Chiou
{"title":"A novel low noise design method for CMOS L-degeneration cascoded LNA","authors":"Sung-Huang Lee, Y. Juang, Chin-Fong Chiu, H. Chiou","doi":"10.1109/APCCAS.2004.1412747","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412747","url":null,"abstract":"The noise optimization design of the CMOS LNA is important in a communication IC. The conventional noise optimization method for L-degeneration cascoded LNA with noise mainly from active device loses the validity as the operating frequency increasing. In this paper, we present a noise optimization with gain matching design method for LNA with fully considerations of noise sources including the induced gate noise and the loss of gate inductor. The gate inductor is an important issue when its quality factor is less than 20","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115613667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Application of dual projected pseudo quasi Newton algorithm in multicommodity network flow problems 对偶投影伪拟牛顿算法在多商品网络流问题中的应用
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412734
Ch'i-Hsin Lin, Shin-Yeu Lin
{"title":"Application of dual projected pseudo quasi Newton algorithm in multicommodity network flow problems","authors":"Ch'i-Hsin Lin, Shin-Yeu Lin","doi":"10.1109/APCCAS.2004.1412734","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412734","url":null,"abstract":"In the paper, we apply a method for solving multicommodity network flow problems, which has important applications in communication networks. This method combines a projected quasi-Newton method and a dual projected pseudo quasi-Newton (DPPQN) method. We use a sparse-block-matrix technique and the finite iteration scaled projection technique to enhance the computational efficiency of DPPQN method. Compared with the Frank-Wolfe with PARTAN algorithm, we show the efficiency of our method by several numerical examples.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114502867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automated phase compensation for multi-stage amplifiers 多级放大器的自动相位补偿
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412958
N. Unno, N. Kusakawa, S. Takagi, N. Fujii
{"title":"Automated phase compensation for multi-stage amplifiers","authors":"N. Unno, N. Kusakawa, S. Takagi, N. Fujii","doi":"10.1109/APCCAS.2004.1412958","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412958","url":null,"abstract":"An automated phase compensation for multi-stage amplifiers using a genetic algorithm (GA) is presented. GA evolves topologies and devise sizes of the compensation circuit to achieve the given specifications. The capability of this method was demonstrated through an experiment of phase compensation for a 4-stage amplifier","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114903705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3D electro-thermal modeling of ggNMOS ESD protection structure ggNMOS ESD保护结构的三维电热建模
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412691
Haolu Xie, R. Zhan, A. Wang, R. Gafiteanu
{"title":"3D electro-thermal modeling of ggNMOS ESD protection structure","authors":"Haolu Xie, R. Zhan, A. Wang, R. Gafiteanu","doi":"10.1109/APCCAS.2004.1412691","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412691","url":null,"abstract":"This work presents a simple-to-implement, 3D electro-thermal model for circuit-level SPICE simulation of grounded-gate NMOS (ggNMOS), with application for ESD (electrostatic discharge) protection circuit design verification. A new ESD discharging fitting resistor (R/sub on/) is employed to improve ESD electrical modeling in the high-current region and a new 3D thermal resistor parameter (R/sub th/) is proposed to model the electro-thermal characteristics of ggNMOS. The extraction method for the new parameters, R/sub on/ and R/sub th/, is discussed. Finally, simulation results are presented and compared with experimental data.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114997608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of reconfigurable carry select adders 可重构进位选择加法器的设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413006
Jin-Fu Li, Yao-Chang Kuo, Chao-Da Huang, Tsu-Wei Tseng, C. Wey
{"title":"Design of reconfigurable carry select adders","authors":"Jin-Fu Li, Yao-Chang Kuo, Chao-Da Huang, Tsu-Wei Tseng, C. Wey","doi":"10.1109/APCCAS.2004.1413006","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413006","url":null,"abstract":"Digital signal processing (DSP) processors for real-time processing of multimedia signals usually include fast reconfrgurable parallel adders for the operations of integers with different precisions. This paper presents a reconfrgurable carry select adder (CSA). High reconfrgurability is achieved with inter-block and intra-block partition schemes. This methodology only causes very small performance penalty and area overhead. Experimental results show that the worst delay ofa 64-bit reconfigurable CSA with eight 8-bit blocks is about 2.4ns based on the TSMC 0.18pm technology. Also, the area overhead ofthe additional partition circuitry is only about 4.6%.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117005839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CMOS RF LNA with high ESD immunity 具有高ESD抗扰度的CMOS RF LNA
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412759
Siu-Keitang, C. Chan, C. Choy, K. Pun
{"title":"CMOS RF LNA with high ESD immunity","authors":"Siu-Keitang, C. Chan, C. Choy, K. Pun","doi":"10.1109/APCCAS.2004.1412759","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412759","url":null,"abstract":"We present a two-stage LNA design with a high ESD immunity. We use a common-gate amplifier as an input stage for our design. The RF input is directly connected to the source of the transistor, which will provide a higher ESD protection than conventional common-source amplifiers. The two-stage LNA is designed to operate at 1.8 GHz with a voltage supply of 1.5 V using AMS 0.35-/spl mu/m CMOS technology. The new LNA has a measured power gain of 14.1 dB with a noise figure of 5 dB. The reverse isolation is -32 dB, and the output-referred third-order intercept point is 6.3 dBm. The measured HBM ESD withstand voltages are 1.5kV and -3.5kV.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116149038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Reconfigurable low power MPEG-4 texture decoder IP design 可重构低功耗MPEG-4纹理解码器IP设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412715
Chien-Chang Lin, Hsiu-Cheng Chang, Jiun-In Guo, Kuan-Hung Chen
{"title":"Reconfigurable low power MPEG-4 texture decoder IP design","authors":"Chien-Chang Lin, Hsiu-Cheng Chang, Jiun-In Guo, Kuan-Hung Chen","doi":"10.1109/APCCAS.2004.1412715","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412715","url":null,"abstract":"We propose a reconfigurable low-power MPEG-4 texture decoder IP design to support up to MPEG-4 SP@L3 video decoding. The proposed texture decoder IP includes an optimized DC/AC prediction and low-power adder-based inverse discrete cosine transform (IDCT) processor. In order to increase the flexibility, the proposed design can be reconfigured to decode MPEG-4 video with different frame sizes without modifying the architecture. For reducing the power consumption, we have re-arranged the MPEG-4 texture decoding flow, exploited efficient adder-based algorithm and DPGC-based architecture for IDCT processor, and adopted the zero vector detection technique in skipping the IDCT operations on zero data. The implementation results show that the proposed texture decoder IP design costs 11698 gates and 9472 bits memory for supporting the MPEG-4 CIF video texture decoding @ 30Hz under the TSMC 0.35/spl mu/m CMOS technology.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116995402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
H.264 decoder optimization exploiting SIMD instructions 利用SIMD指令的H.264解码器优化
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413088
Juyup Lee, Sungkun Moon, Wonyong Sung
{"title":"H.264 decoder optimization exploiting SIMD instructions","authors":"Juyup Lee, Sungkun Moon, Wonyong Sung","doi":"10.1109/APCCAS.2004.1413088","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413088","url":null,"abstract":"In this paper, H.264/AVC, the newest video coding standard, baseline profile decoder was implemented exploiting Intel MMX instructions. Both control- and data-level parallel processing approaches'were applied to the kernels of the baseline subsystems for efficiently utilizing the SIMD (Single Instruction Multiple Data) instructions. The data-level parallel approach tries to process multiple pixels at a time to fully utilize SIMD instructions. The data-level approach shows a better performance even though loop unrolling is further applied to the conlrol-level approach. The resultant implementations are also compared with the Intel Performance Primitives.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117079384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance study of multi-channel multicast delivery for scheduled videos 定时视频多通道多播传输性能研究
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413025
Chow-Sing Lin, Tzong-Yao Chang, Fang-Zhi Yen
{"title":"Performance study of multi-channel multicast delivery for scheduled videos","authors":"Chow-Sing Lin, Tzong-Yao Chang, Fang-Zhi Yen","doi":"10.1109/APCCAS.2004.1413025","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413025","url":null,"abstract":"In reality, not all users require instant video access. People are used to planning things ahead, surely including when to watch desired videos. This fact creates the new video scheduling paradigm, named scheduled video delivery (SVD). It allures clients to make requests as early as possible in order to increase the flexibility of stream scheduling and resource utilization based on pricing. We provide a performance study of our proposed multi-channel multicast delivery (MCMD) scheduling algorithm for SVD. MCMD fully utilizes the multi-channel receiving capability of the clients to improve the resource utilization and the degree of multicast in delivering continuous media. The performance study of its scheduling behavior shows that MCMD produces lower rejection rate and requires fewer number of channels to have no rejections than the existing MEDF and LPF on SVD.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123939703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A bit-allocation model using on-line rate-distortion optimization in MPEG-4 rate control 基于在线率失真优化的MPEG-4码率分配模型
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412712
Zhongwei Zhang, Guizhong Liu, Yongli Li, M. Zhang
{"title":"A bit-allocation model using on-line rate-distortion optimization in MPEG-4 rate control","authors":"Zhongwei Zhang, Guizhong Liu, Yongli Li, M. Zhang","doi":"10.1109/APCCAS.2004.1412712","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412712","url":null,"abstract":"In typical video coding, the rate control allocates a target number of bits to each frame and selects the quantization parameters to meet the frame targets. To produce a consistent picture quality between consecutive frames, we propose a new technique for assigning such targets using the Lagrange multiplier method. The proposed bit-allocation algorithm is applied to improve MPEG-4 Q2 rate-control scheme. Simulation results show that the improved Q2 scheme not only achieves 0.42-0.54 dB PSNR gain but maintains a very consistent quality.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125858506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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