2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献

Robust In-Memory Computing with Hyperdimensional Stochastic Representation 基于超维随机表示的鲁棒内存计算

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642237

Prathyush Poduval, Mariam Issa, Farhad Imani, Cheng Zhuo, Xunzhao Yin, M. Najafi, M. Imani

引用次数: 2

Fuzzing Hardware: Faith or Reality? : Invited Paper 模糊硬件:信念还是现实?:特邀论文

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642252

Weimin Fu, Orlando Arias, Yier Jin, Xiaolong Guo

引用次数: 0

A Review of Deterministic Approaches to Stochastic Computing 随机计算的确定性方法综述

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642242

Zhendong Lin, Guangjun Xie, Shaowei Wang, Jie Han, Yongqiang Zhang

{"title":"A Review of Deterministic Approaches to Stochastic Computing","authors":"Zhendong Lin, Guangjun Xie, Shaowei Wang, Jie Han, Yongqiang Zhang","doi":"10.1109/NANOARCH53687.2021.9642242","DOIUrl":"https://doi.org/10.1109/NANOARCH53687.2021.9642242","url":null,"abstract":"Stochastic computing (SC) has emerged as an alternative to conventional computing with weighted binary representation. The operations in SC can be performed through simple logic gates to significantly reduce hardware complexity. The random bitstreams generated by stochastic number generators are exploited as the computing medium in SC. However, traditional operations in SC are inaccurate because of the inherent random fluctuations in bitstreams. To resolve this issue, deterministic approaches using the relatively prime stream length, rotation, and clock division of bitstreams, have been proposed for completely accurate computing. However, these approaches require much longer bitstreams, resulting in a longer computing latency and thus a larger energy consumption. For example, the bitstream length (BSL) is approximately 22n if two numbers with n-bit precision are multiplied using a deterministic approach. The studies aimed at lowering the latency and energy can be divided into two categories of serial and parallel designs to, respectively, reduce the BSL and parallelize bitstreams. These deterministic approaches to SC and the associated designs are reviewed in this paper with discussions of their strengths and weaknesses for possible improvements in future work.","PeriodicalId":424982,"journal":{"name":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122725796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Dynamically Configurable Physical Unclonable Function based on RRAM Crossbar 基于RRAM横杆的动态可配置物理不可克隆功能

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642245

Jiang Li, Yijun Cui, Chongyan Gu, Chenghua Wang, Weiqiang Liu

{"title":"Dynamically Configurable Physical Unclonable Function based on RRAM Crossbar","authors":"Jiang Li, Yijun Cui, Chongyan Gu, Chenghua Wang, Weiqiang Liu","doi":"10.1109/NANOARCH53687.2021.9642245","DOIUrl":"https://doi.org/10.1109/NANOARCH53687.2021.9642245","url":null,"abstract":"Physical unclonable function (PUF) has been an effective solution for hardware security with the popularity of the internet of things (IoT). Due to low power consumption and high area efficiency, an emerging nonvolatile memory, resistive random access memory (RRAM) based PUF designs have attracted many attentions. Due to the bottleneck in the existing RRAM PUFs that it can not be fully compatible with the memory architecture, a dynamically configurable PUF based on the mainstream RRAM crossbar is proposed in this paper. Utilizing the device-to-device variation of the RRAM resistance, abundant challenge-response pairs (CRPs) are generated with a flexible configuration of an RRAM crossbar. Furthermore, different from the existing RRAM-based PUF designs, the proposed RRAM PUF can be dynamically configured between a memory cell and a PUF cell, without requiring additional sense circuits, leading to a minimal design overhead. The simulation results show that the proposed PUF exhibits good performance with a high uniqueness and reliability. Moreover, it achieves a great resistance against machine learning (ML) attack.","PeriodicalId":424982,"journal":{"name":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131484361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Commutative Approximate Adders: Analysis and Evaluation 交换近似加法器:分析与评价

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642233

Junqi Huang, T. N. Kumar, Haider A. F. Almurib, F. Lombardi

{"title":"Commutative Approximate Adders: Analysis and Evaluation","authors":"Junqi Huang, T. N. Kumar, Haider A. F. Almurib, F. Lombardi","doi":"10.1109/NANOARCH53687.2021.9642233","DOIUrl":"https://doi.org/10.1109/NANOARCH53687.2021.9642233","url":null,"abstract":"Ripple Carry Adders (RCAs) made of approximate cells are used in many applications to reduce power dissipation and delay. Unlike its exact counterpart, an approximate RCA may have a non-commutative feature due to the characteristics of the approximate cells. This paper analyses the commutative property of approximate RCAs. Initially, the Boolean equations and state diagram of approximate cells in the design of RCA are presented and conditions for an approximate cell to compute a non-commutative addition (NCA) are provided. The analysis shows that only a few approximate adders do not affect the commutative property. Then, an extensive analysis using images from a public library is performed by considering two-image addition. As expected, the non-commutative operation causes variations in the quality of output images; performance metrics such as PSNR, MED (Mean Error Distance) and MaxED (Maximum Error Distance) vary as the inputs are reversed. The results show that the absolute difference of PSNR, MED and MaxED (DPSNR, DMED, DMaxED) by reversing the inputs for non-commutative adders increases when the number of applied approximate cells increases. Among the non-commutative approximate adders, AMA3 has the lowest average DPSNR and DMaxED, 54% and 43% (to the maximum) of the highest one (AMA4). The average DMED for AMA4 is also the highest, so 9.23 and 2 times higher than AMA1 and AMA3 respectively.","PeriodicalId":424982,"journal":{"name":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132713893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication STT-MRAM中串行位元的内存计算方案，实现高效的多位模拟乘法

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642248

Zuolei Hao, Yue Zhang, Jinkai Wang, Hongyu Wang, Yining Bai, Guanda Wang, Weisheng Zhao

{"title":"A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication","authors":"Zuolei Hao, Yue Zhang, Jinkai Wang, Hongyu Wang, Yining Bai, Guanda Wang, Weisheng Zhao","doi":"10.1109/NANOARCH53687.2021.9642248","DOIUrl":"https://doi.org/10.1109/NANOARCH53687.2021.9642248","url":null,"abstract":"Computing-in-memory (CIM) is widely studied to solve the Von Neumann bottleneck, which improves energy-efficient computing. In this work, we propose a CIM with series bit-cell (SBCIM) scheme, which can perform the multi-bit analog multiplication in spin-transfer torque magnetic random access memory (STT-MRAM). Utilizing the proposed bit-cell structure consisting of three transistors and one magnetic tunnel junction (MTJ), multiple bit-cells on a column can be connected in series to overcome the inherent low on/off ratio of MTJ in CIM. Then, by converting the input data into a current injected into bit-line and the bit-line voltage into time-domain, the multiplication of two 2-bit numbers is implemented. In addition, a difference gain (DG) circuit is also designed to increase the difference of the signal representing the multiplication value, which achieves the multiplication of two 3-bit numbers. Simulation results show that the signal margin in our scheme is 10~200 times higher than that of conventional memory array in CIM schemes. Meanwhile, compared with the Spintronic Processing Unit (SPU) scheme, the delay and energy of Multiply Accumulate (MAC) operation in SBCIM scheme have been improved by 60 times and 8.8 times under 3-bit precision, respectively.","PeriodicalId":424982,"journal":{"name":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116281902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Hybrid MTJ-CMOS Integration for Sigma-Delta ADC 用于Sigma-Delta ADC的混合MTJ-CMOS集成

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642236

Yuanyuan Wu, L. Naviner, Hao Cai

引用次数: 1

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch 基于多节点扰动的六重交叉耦合双互锁存储单元自恢复锁存器

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642250

Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Tianming Ni, Zhengfeng Huang, X. Wen

引用次数: 2

RRAM-based Analog In-Memory Computing : Invited Paper 基于随机存储器的模拟内存计算:特邀论文

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642235

Xiaoming Chen, Tao Song, Yinhe Han

{"title":"RRAM-based Analog In-Memory Computing : Invited Paper","authors":"Xiaoming Chen, Tao Song, Yinhe Han","doi":"10.1109/NANOARCH53687.2021.9642235","DOIUrl":"https://doi.org/10.1109/NANOARCH53687.2021.9642235","url":null,"abstract":"Despite resistive random-access memories (RRAMs) have the ability of analog in-memory computing and they can be utilized to accelerate some applications (e.g., neural networks), the analog-digital interface consumes considerable overhead and may even counteract the benefits brought by RRAM-based inmemory computing. In this paper, we introduce how to reduce or eliminate the overhead of the analog-digital interface in RRAM-based neural network accelerators and linear solver accelerators. In the former, we create an analog inference flow and introduce a new methodology to accelerate the entire analog flow by using resistive content-addressable memories (RCAMs). Redundant analog-to-digital conversions are eliminated. In the latter, we provide an approach to map classical iterative solvers onto RRAM-based crossbar arrays such that the hardware can get the solution in O(1) time complexity without actual iterations, and thus, intermediate analog-to-digital conversions and digital-to-analog conversions are completely eliminated. Simulation results have proven the superiorities in the performance and energy efficiency of our approaches. The accuracy problem of RRAM-based analog computing will be a future research focus.","PeriodicalId":424982,"journal":{"name":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114089825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Experimental Verification of EMPA Fault Mechanism EMPA故障机理的实验验证

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2021-11-08 DOI: 10.1109/NANOARCH53687.2021.9642244

Maoshen Zhang, Qiang Liu

{"title":"Experimental Verification of EMPA Fault Mechanism","authors":"Maoshen Zhang, Qiang Liu","doi":"10.1109/NANOARCH53687.2021.9642244","DOIUrl":"https://doi.org/10.1109/NANOARCH53687.2021.9642244","url":null,"abstract":"The efficient fault injection attack (FIA) technique, electromagnetic pulse attack (EMPA), is the serious threat to the security of integrated circuits (ICs). To protect ICs against EMPA, it is necessary to understand EMPA fault mechanism. In this paper, a widely accepted hypothesis suggests that the faults are induced by the disturbances, caused by the EMPA, on the power/ground grids in ICs. The goal of this work is to verify the hypothesis by experiments. A coupling model of EMPA is first presented based on the Faraday’s law and the hypothesis. The influence of EMPA on the power/ground grids is predicted with the model. Then an experiment is designed, where inverters are used to monitor the disturbances on the power/ground grids when EMPA with various parameters is performed. A physical EMPA platform is built and a circuit with inverter chain is fabricated in 0.11um technology. The experimental results show that the disturbances on the power/ground grids are closely related to the EMPA pulses, in accordance to the prediction. The results, on the one hand, demonstrate the reasonability of the hypothesis and on the other hand reveal that the influence of EMPA on the carriers of CMOS gates in the attacked circuit should be also considered for the precise analysis about the EMPA fault mechanism.","PeriodicalId":424982,"journal":{"name":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129673347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1