{"title":"基于多节点扰动的六重交叉耦合双互锁存储单元自恢复锁存器","authors":"Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Tianming Ni, Zhengfeng Huang, X. Wen","doi":"10.1109/NANOARCH53687.2021.9642250","DOIUrl":null,"url":null,"abstract":"As transistor feature sizes continue to scale down, the susceptibility of integrated circuits to harsh-radiation induced multiple-node-upsets (MNUs), such as double-node upsets (DNUs) and triple-node upsets (TNUs), is increasing. This paper presents an MNU self-recoverable hardened latch (namely SCDMSH) based on sextuple cross-coupled dual-interlocked-storage-cells (DICEs). The latch consists of eight transmission gates and six interlocked DICE cells. Due to the interlocking mechanism constructed from single-node-upset-self-recoverable DICE cells, the latch can self-recover from any possible single node upset (SNU), DNU and TNU. Simulation results validate the SNU, DNU and TNU self-recoverability of the proposed latch. Simulation results also demonstrate that the SCDMSH latch can approximately save 49% silicon area at the cost of moderate delay and power, compared with the state-of-the-art TNU self-recoverable reference latch (TNURL) of the same-type.","PeriodicalId":424982,"journal":{"name":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch\",\"authors\":\"Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Tianming Ni, Zhengfeng Huang, X. Wen\",\"doi\":\"10.1109/NANOARCH53687.2021.9642250\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As transistor feature sizes continue to scale down, the susceptibility of integrated circuits to harsh-radiation induced multiple-node-upsets (MNUs), such as double-node upsets (DNUs) and triple-node upsets (TNUs), is increasing. This paper presents an MNU self-recoverable hardened latch (namely SCDMSH) based on sextuple cross-coupled dual-interlocked-storage-cells (DICEs). The latch consists of eight transmission gates and six interlocked DICE cells. Due to the interlocking mechanism constructed from single-node-upset-self-recoverable DICE cells, the latch can self-recover from any possible single node upset (SNU), DNU and TNU. Simulation results validate the SNU, DNU and TNU self-recoverability of the proposed latch. Simulation results also demonstrate that the SCDMSH latch can approximately save 49% silicon area at the cost of moderate delay and power, compared with the state-of-the-art TNU self-recoverable reference latch (TNURL) of the same-type.\",\"PeriodicalId\":424982,\"journal\":{\"name\":\"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-11-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NANOARCH53687.2021.9642250\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANOARCH53687.2021.9642250","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch
As transistor feature sizes continue to scale down, the susceptibility of integrated circuits to harsh-radiation induced multiple-node-upsets (MNUs), such as double-node upsets (DNUs) and triple-node upsets (TNUs), is increasing. This paper presents an MNU self-recoverable hardened latch (namely SCDMSH) based on sextuple cross-coupled dual-interlocked-storage-cells (DICEs). The latch consists of eight transmission gates and six interlocked DICE cells. Due to the interlocking mechanism constructed from single-node-upset-self-recoverable DICE cells, the latch can self-recover from any possible single node upset (SNU), DNU and TNU. Simulation results validate the SNU, DNU and TNU self-recoverability of the proposed latch. Simulation results also demonstrate that the SCDMSH latch can approximately save 49% silicon area at the cost of moderate delay and power, compared with the state-of-the-art TNU self-recoverable reference latch (TNURL) of the same-type.