A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication

Abstract

Computing-in-memory (CIM) is widely studied to solve the Von Neumann bottleneck, which improves energy-efficient computing. In this work, we propose a CIM with series bit-cell (SBCIM) scheme, which can perform the multi-bit analog multiplication in spin-transfer torque magnetic random access memory (STT-MRAM). Utilizing the proposed bit-cell structure consisting of three transistors and one magnetic tunnel junction (MTJ), multiple bit-cells on a column can be connected in series to overcome the inherent low on/off ratio of MTJ in CIM. Then, by converting the input data into a current injected into bit-line and the bit-line voltage into time-domain, the multiplication of two 2-bit numbers is implemented. In addition, a difference gain (DG) circuit is also designed to increase the difference of the signal representing the multiplication value, which achieves the multiplication of two 3-bit numbers. Simulation results show that the signal margin in our scheme is 10~200 times higher than that of conventional memory array in CIM schemes. Meanwhile, compared with the Spintronic Processing Unit (SPU) scheme, the delay and energy of Multiply Accumulate (MAC) operation in SBCIM scheme have been improved by 60 times and 8.8 times under 3-bit precision, respectively.