Proceedings of 14th VLSI Test Symposium最新文献_第7页

Synthesis-for-scan and scan chain ordering 扫描合成和扫描链排序

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510840

R. Norwood, E. McCluskey

引用次数: 22

Testing "untestable" faults in three-state circuits 在三态电路中测试“不可测试”的故障

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510875

P. Wohl, J. Waicukauski, M. Graf

引用次数: 14

On completely robust path delay fault testable realization of logic functions 对完全鲁棒路径延迟故障逻辑函数的可测试性实现

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510872

V. Vardanian

引用次数: 1

Self-dual parity checking-A new method for on-line testing 自对偶奇偶校验——在线测试的一种新方法

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510852

V. Saposhnikov, A. Dmitriev, M. Gössel, V. Saposhnikov

引用次数: 31

An analysis of fault partitioning algorithms for fault partitioned ATPG 故障分区ATPG故障分区算法分析

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510862

R. Klenke, J. Aylor, Joseph M. Wolf

{"title":"An analysis of fault partitioning algorithms for fault partitioned ATPG","authors":"R. Klenke, J. Aylor, Joseph M. Wolf","doi":"10.1109/VTEST.1996.510862","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510862","url":null,"abstract":"Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of generating test vectors is an promising area of research. The simplest approach to parallelization of the test generation process is to simply divide the processing of the fault list across multiple processors. Each individual processor then performs the normal rest generation process on its own portion of the fault list, typically without interaction with the other processors. The major drawback of this technique, called fault partitioning, is that the processors perform redundant work generating test vectors for faults covered by vectors generated on another processor. This problem has been solved with the introduction of dynamic load balancing and detected fault broadcasting. Previous research has indicated that algorithmic fault partitioning moderately improves the performance of fault partitioned ATPG without detected fault broadcasting by reducing redundant work. However algorithmic fault partitioning can add significant preprocessing time to the ATPG process. This paper presents results that show that algorithmic partitioning is unnecessary prior to fault partitioned parallel ATPG using detected fault broadcasting and dynamic load balancing. Considering preprocessing time, random fault partitioning is shown to be the most efficient technique for partitioning faults prior to fault partitioned ATPG.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130440653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads H-SCAN:全面扫描测试的高级替代方案，减少了面积和测试应用开销

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510838

S. Bhattacharya, S. Dey

引用次数: 50

Quantitative analysis of very-low-voltage testing 极低压试验的定量分析

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510876

J. Chang, E. McCluskey

引用次数: 64

Optimal voltage testing for physically-based faults 物理故障的最佳电压测试

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510878

Y. Liao, D.M.H. Walker

引用次数: 20

Implicit functional testing for analog circuits 模拟电路的隐式功能测试

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510898

Chen-Yang Pan, K. Cheng

引用次数: 39

On the (non-)resetability of synchronous sequential circuits 同步顺序电路的(非)可复位性

Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510863

Martin Keim, B. Becker, Birgitta Stenner

引用次数: 23