{"title":"对完全鲁棒路径延迟故障逻辑函数的可测试性实现","authors":"V. Vardanian","doi":"10.1109/VTEST.1996.510872","DOIUrl":null,"url":null,"abstract":"A large class of Boolean functions, as well as almost all symmetric Boolean functions, are shown to have no two-level completely robust path-delay-fault testable (RPDFT) realization by combinational circuits. Exact and asymptotic formulae are derived for the number of symmetric Boolean functions which have two-level completely RPDFT realization. To achieve completely RPDFT realization, a notion of RPDFT-extension is proposed for logic functions which have no two-level completely RPDFT realization. Algorithms are devised for the design of RPDFT-extensions with at most 2 extra input variables.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On completely robust path delay fault testable realization of logic functions\",\"authors\":\"V. Vardanian\",\"doi\":\"10.1109/VTEST.1996.510872\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A large class of Boolean functions, as well as almost all symmetric Boolean functions, are shown to have no two-level completely robust path-delay-fault testable (RPDFT) realization by combinational circuits. Exact and asymptotic formulae are derived for the number of symmetric Boolean functions which have two-level completely RPDFT realization. To achieve completely RPDFT realization, a notion of RPDFT-extension is proposed for logic functions which have no two-level completely RPDFT realization. Algorithms are devised for the design of RPDFT-extensions with at most 2 extra input variables.\",\"PeriodicalId\":424579,\"journal\":{\"name\":\"Proceedings of 14th VLSI Test Symposium\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 14th VLSI Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1996.510872\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 14th VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1996.510872","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On completely robust path delay fault testable realization of logic functions
A large class of Boolean functions, as well as almost all symmetric Boolean functions, are shown to have no two-level completely robust path-delay-fault testable (RPDFT) realization by combinational circuits. Exact and asymptotic formulae are derived for the number of symmetric Boolean functions which have two-level completely RPDFT realization. To achieve completely RPDFT realization, a notion of RPDFT-extension is proposed for logic functions which have no two-level completely RPDFT realization. Algorithms are devised for the design of RPDFT-extensions with at most 2 extra input variables.
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