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A new geometric approach to mobile position in wireless LAN reducing complex computations 一种新的无线局域网移动定位几何方法，减少了复杂的计算
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487566
M. Zaidi, R. Tourki, R. Ouni
{"title":"A new geometric approach to mobile position in wireless LAN reducing complex computations","authors":"M. Zaidi, R. Tourki, R. Ouni","doi":"10.1109/DTIS.2010.5487566","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487566","url":null,"abstract":"Positions estimation from Time of Arrival (TOA), Time Difference of Arrival (TDOA), and Angle of Arrival (AOA) measurements are the commonly used techniques. These approaches use the location parameters received from different sources and they are based on intersections of circles, hyperbolas, and lines, respectively. The location is determined using standard complex computation methods that are usually implemented in software and needed relatively long execution time. An important factor in achieving this is to minimize and simplify the instructions that the mobile station (MS) has to execute in the location determination process. Finding an effective location estimation technique to facilitate processing data is the main focuses in this paper. Therefore, in the wireless propagation environment the Received Signal Strength (RSS) information from three base stations (BSs) are recorded and processed and they can provide an overlapping coverage area of interest. Then an easy geometric technique is applied in order to effectively calculate the location of the desired MS.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130299392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design and FPGA implementation of modular multiplication methods using cellular automata 基于元胞自动机的模块化乘法方法的设计与FPGA实现
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487586
Z. Guitouni, R. Chotin-Avot, Mohsen Machhout, H. Mehrez, R. Tourki
{"title":"Design and FPGA implementation of modular multiplication methods using cellular automata","authors":"Z. Guitouni, R. Chotin-Avot, Mohsen Machhout, H. Mehrez, R. Tourki","doi":"10.1109/DTIS.2010.5487586","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487586","url":null,"abstract":"Cellular automata (CA) have been accepted as a good evolutionary computational model for the simulation of complex physical systems. They have been used for various applications, such as parallel processing computations and number theory. In this paper, we studied the applications of cellular automata for the modular multiplications; we proposed two new architectures of multipliers based on cellular automata over finite field GF(2m). Since they have regularity, modularity and concurrency, they are suitable for VLSI implementation. The proposed architectures can be easily implemented into the hardware design of crypto-coprocessors.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129653484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new built-in self-test (BIST) for a RF low-noise amplifier (LNA) 一种新的射频低噪声放大器(LNA)内置自检(BIST)方法
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487559
R. Ayadi, M. Masmoudi
{"title":"A new built-in self-test (BIST) for a RF low-noise amplifier (LNA)","authors":"R. Ayadi, M. Masmoudi","doi":"10.1109/DTIS.2010.5487559","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487559","url":null,"abstract":"In this paper, we present a new RF built-in self test (BIST) circuit for 865–870 MHz low noise amplifiers (LNAs); The BIST and LNA circuit is designed using 0.35µm CMOS technology. The simple circuit of test that contains a RF peak detectors and two comparators brings high fault coverage. The faults simulating possible catastrophic and parametric faults are introduced. A total of twenty eight short and open faults and ten parameters variation have been introduced into the LNA, giving fault coverage of 89% for catastrophic faults and 90% for process variation.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129917327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation of deep levels in AlGaN/GaN HEMTs on silicon substrate by conductance deep level transient spectroscopy 用电导深能级瞬态光谱研究硅衬底上AlGaN/GaN HEMTs的深能级
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487570
H. Mosbahi, M. Gassoumi, M. Charfeddine, C. Gaquière, M. A. Zaidi, H. Maaref
{"title":"Investigation of deep levels in AlGaN/GaN HEMTs on silicon substrate by conductance deep level transient spectroscopy","authors":"H. Mosbahi, M. Gassoumi, M. Charfeddine, C. Gaquière, M. A. Zaidi, H. Maaref","doi":"10.1109/DTIS.2010.5487570","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487570","url":null,"abstract":"We report investigation of electron traps in AlGaN/GaN HEMTs, grown on silicon by molecular beam epitaxy. Deep levels analysis was performed by conductance deep level transient spectroscopy (CDLTS) under a drain pulse. CDLTS measurements reveal three traps with the energy levels of 0.11, 0.17 and 0.22 eV.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131155729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of Speaker Identification System using GSMEFR speech Data 基于GSMEFR语音数据的说话人识别系统评价
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487589
Ahmed Krobba, M. Debyeche, A. Amrouche
{"title":"Evaluation of Speaker Identification System using GSMEFR speech Data","authors":"Ahmed Krobba, M. Debyeche, A. Amrouche","doi":"10.1109/DTIS.2010.5487589","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487589","url":null,"abstract":"This paper investigate the influence of GSMEFR speech Data on the performance of a text independent Speaker Identification System (SIS) based on Gaussian Mixture Models (GMM) classifiers. The performance evaluation due to the use of the GSMEFR speech Data, obtained by passing the local ARADIGIT database through the GSM coder/decoder. The recognition evaluation was also conducted using original ARADIGIT sampled at 16 KHz and its 8 KHz downsampled version. The ARADIGIT database consists of 60 speakers (31 men and 29 women) pronouncing the ten Arabic digits three times each. Different experiments were carried to measure the degradation introduced by different aspects of the simulated codec.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124296929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A method of unsensitizable path identification using high level design information 一种利用高层次设计信息的不敏感路径识别方法
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487557
S. Ohtake, Naotsugu Ikeda, M. Inoue, H. Fujiwara
{"title":"A method of unsensitizable path identification using high level design information","authors":"S. Ohtake, Naotsugu Ikeda, M. Inoue, H. Fujiwara","doi":"10.1109/DTIS.2010.5487557","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487557","url":null,"abstract":"This paper proposes a method of unsensitizable path identification. By dealing with untestable paths in sequential circuits at register-transfer level (RTL) and utilizing design information obtained from high-level synthesis, the method can identify sequentially unsensitizable paths effectively and efficiently. Information about identified unsensitizable paths can not only facilitate process of test generation but also mitigate futileness of testing. In this work, we employ non-robust unsensitizability, which is widely supported in current ATPG systems, for identifying unsensitizable paths. We show the effectiveness of use of high-level design information through our experiments using RTL circuits synthesized from behavioral benchmark circuits.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115207568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Hight fault tolerance in neural crossbar 神经横杆的高容错性
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-01 DOI: 10.1109/DTIS.2010.5487552
Djaafar Chabi, Jacques-Olivier Klein
{"title":"Hight fault tolerance in neural crossbar","authors":"Djaafar Chabi, Jacques-Olivier Klein","doi":"10.1109/DTIS.2010.5487552","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487552","url":null,"abstract":"Proposed nanometer-scale electronic devices are generally expected to feature an increased probability of manufacturing defects. We present in this paper a novel, highly fault-tolerant architecture, based on memristor crossbar architecture that may enable reliable implementation of neural network. Simulation results of our learning method inspired of Delta rule [1] for monolayer crossbar, exhibits very fast convergence rate to learn Boolean functions. In addition we simulate the impact of defects to measure the ability of our architecture to repair defective neurons, using a competitive learning scheme with or without redundancy. The architecture is able to learn the Boolean functions with manufacturing defect rate up to 13% with reasonable redundancy amount. It shows the best fault-tolerance performance comparing with the other techniques like RMR, von Neumann multiplexing and reconfiguration.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125050748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Surface- potential- based model to study the subthreshold swing behavior including hot-carrier effect for nanoscale GASGAA MOSFETs 基于表面电位的模型研究了纳米级GASGAA mosfet的亚阈值摆动行为，包括热载子效应
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410884
D. Faycal, A. Mohamed Amir, A. Djemai, B. Toufik
{"title":"Surface- potential- based model to study the subthreshold swing behavior including hot-carrier effect for nanoscale GASGAA MOSFETs","authors":"D. Faycal, A. Mohamed Amir, A. Djemai, B. Toufik","doi":"10.1109/ICECS.2009.5410884","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410884","url":null,"abstract":"The proper design and simulation of future nanoelectronics digital devices requires accurate models of subthreshold behavior. The Gate All Around (GAA) MOSFET is considered one the most promising devices for downscaling below 50 nm. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the long-term stability of subthreshold performances in a nanoscale MOS transistor. Therefore, in this paper an analytical, surface-potential-based, model for the subthreshold swing of undoped GAA MOSFETs has been derived at low drain-source voltage based on an analytical solution of the two-dimensional Poisson equation (in cylindrical coordinates) with the hot carrier term included. The new model has been verified by comparison with 2-D numerical simulations.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126514136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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