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An embedded system for iris recognition 用于虹膜识别的嵌入式系统
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487592
Raida Hentati, M. Bousselmi, M. Abid
{"title":"An embedded system for iris recognition","authors":"Raida Hentati, M. Bousselmi, M. Abid","doi":"10.1109/DTIS.2010.5487592","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487592","url":null,"abstract":"Several systems require authenticating a person's identity before giving access to resources. With new advances in technology, biometrics is one of the most promising techniques in human recognition. Biometrics intends to identify a person by his physical and/or behavioural characteristics. This paper presents an approach for human authentication based on iris texture analysis. In this paper, we present a HW/SW implementation algorithm for detection and localisation of iris based on shape properties. The designed system has been implemented in a CYCLONE II DE2 Board using the NIOS II processor which is characterized by its flexibility and programmability. The data base CASIA version 1.0 is used for the test. The experimental results of the approach show the performance of our algorithms.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On the embedded vector RF measurements in frequency agile and reconfigurable front-ends 频率捷变可重构前端嵌入式矢量射频测量研究
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487547
A. Kouki, I. Masri, F. Gagnon, C. Thibeault
{"title":"On the embedded vector RF measurements in frequency agile and reconfigurable front-ends","authors":"A. Kouki, I. Masri, F. Gagnon, C. Thibeault","doi":"10.1109/DTIS.2010.5487547","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487547","url":null,"abstract":"Emerging intelligent and reconfigurable radiofrequency front-ends require the use of embedded vector measurements to ensure their proper tuning and operation at the frequency of choice. Alternative solutions for embedded vector measurements are briefly reviewed and a new wideband, non directional four-port reflectometer for vector reflection coefficient measurement is proposed. The four-port is based on two nondirectional low coupling RF samplers judiciously placed on a transmission line. The principle and the basic theory governing the 4-port operation are presented. Experimental measurements using the proposed reflectometer are compared to simulations as well as measurements using commercial vector network analyzers for a wide range of loads. Good agreement is obtained with an error not exceeding 0.8 dB6∠6°.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127426254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and implementation of network interface compatible OCP For packet based NOC 基于分组的网络接口兼容OCP的设计与实现
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487541
Brahim attia abdelkrim zitouni, R. Tourki
{"title":"Design and implementation of network interface compatible OCP For packet based NOC","authors":"Brahim attia abdelkrim zitouni, R. Tourki","doi":"10.1109/DTIS.2010.5487541","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487541","url":null,"abstract":"The idea of using on chip packet switched networks for Interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) go in developing interfaces for connecting cores to the on-chip network. Standardization of interfaces for these cores such OCP [1] can speed up the development process.In this paper, we present our work of developing a Network Interface for an on-chip network that support OCP IP standard. We chose a range of IP OCP that need to support basic and precise burst mode extension for design an effective. Any cores IP having this configuration can reuse this network interface. Finnaly we will present a comparative study between two Master Network Adaptator and tow Slave Network Adaptator that use respectively handshake and credit based control flow.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128575533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
High level optimization of a MSK modulator using Hoke_D4 experimental design 基于Hoke_D4实验设计的MSK调制器高层优化
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487602
S. Sahnoun, A. Fakhfakh, N. Masmoudi, H. Levi
{"title":"High level optimization of a MSK modulator using Hoke_D4 experimental design","authors":"S. Sahnoun, A. Fakhfakh, N. Masmoudi, H. Levi","doi":"10.1109/DTIS.2010.5487602","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487602","url":null,"abstract":"The purpose of this work is to design a MSK modulator capable to work at a high data modulation. To achieve a low simulation runtime, the modulator is described in VHDL-AMS hardware description language. It is optimized by applying the “Hoke_D4 experimental design” with five factors having in view to minimize the modulator response time. An optimum solution is performed with the help of NEMROD software.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130902303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA implementation of vector directional distance filter FPGA实现矢量方向距离滤波器
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487600
A. Boudabous, A. Ben Atitallah, L. Khriji, P. Kadionik, N. Masmoudi
{"title":"FPGA implementation of vector directional distance filter","authors":"A. Boudabous, A. Ben Atitallah, L. Khriji, P. Kadionik, N. Masmoudi","doi":"10.1109/DTIS.2010.5487600","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487600","url":null,"abstract":"In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best execution time. After validation, using NiosII development board, we demonstrate a clearly improvement in the filtering speed compared to the software solution. Experiments on a large and diverse image sets show that our implementation approach achieves an excellent balance between simplicity, accuracy, and computational speed.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
PI-like fuzzy control implementation using FPGA technology 采用FPGA技术实现类pi模糊控制
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487595
A. Azzouna, A. Sakly, A. Trimeche, A. Mtibaa, M. Benrejeb
{"title":"PI-like fuzzy control implementation using FPGA technology","authors":"A. Azzouna, A. Sakly, A. Trimeche, A. Mtibaa, M. Benrejeb","doi":"10.1109/DTIS.2010.5487595","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487595","url":null,"abstract":"This paper proposes the design of PI-like fuzzy logic controller (PIFLC), on Field Programmable Gate Array (FPGA) device which improve speed, accuracy, power, compactness, and cost effectiveness. The design utilizes 1260 slices of the target FPGA, and is able to produce an output at 6µs. The proposed controller is tested with a first order system. The experimental results were compared to the simulation ones obtained with the toolbox SIMULINK of MATLAB.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134623142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Electrical simulation of learning stage in OG-CNTFET based neural crossbar 基于OG-CNTFET的神经杆学习阶段的电模拟
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487555
Jean-Marie Retrouvey, Jacques-Olivier Klein, Si-Yu Liao, C. Maneux
{"title":"Electrical simulation of learning stage in OG-CNTFET based neural crossbar","authors":"Jean-Marie Retrouvey, Jacques-Olivier Klein, Si-Yu Liao, C. Maneux","doi":"10.1109/DTIS.2010.5487555","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487555","url":null,"abstract":"As the fabrication cost of CMOS mask increases exponentially while the technology is approaching its physical limits, research interest focuses on emerging technologies and alternative architectures. Non-volatile components are considered as possible alternative technologies and neural networks constitute an interesting framework. Here, we present a learning strategy applied to a new non volatile device: the Optically Gated Carbon Nanotube Field Effect Transistor (OG-CNTFET). In this paper, electrical simulations using accurate compact model demonstrate the efficiency of this method to learn linearly separable Boolean functions.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"104 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134458055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Modelling of sigma-delta converters in SystemC for the electromechanical systems control SystemC中用于机电系统控制的σ - δ变换器建模
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487551
Riadh Saidia, S. Ben Saoud
{"title":"Modelling of sigma-delta converters in SystemC for the electromechanical systems control","authors":"Riadh Saidia, S. Ben Saoud","doi":"10.1109/DTIS.2010.5487551","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487551","url":null,"abstract":"In this paper, we expose the design and implementation stages of sigma-delta converters based on over-sampling techniques by using the specification tool SystemC. We used SystemC as simulation tool of hardware systems to test sigma-delta converters based on fir (finite impulse response) decimation filter. The converters validation is realized on a regulation system for a DC-motor. The interest of these converters is the use of an important sampling rate compared to the variables system dynamic of the modeled system which induces: - Increase in the resolution of the acquired or restored data. - Attenuation of the quantification noises. - Simplification of anti-aliasing filters implementation. In the context of SOC design's methodologies improvement, we also describe the specification of a numerical control system at various abstraction levels. In particular, this specification is carried out for the levels of abstraction TLM (Transaction Level Model) and RTL (Register Transfer Level). The specification approach in the regulator's design can be extended to other electromechanical processes. We carried out the specification of the regulator by using SystemC since this tool allows the specification of numerical systems on TLM abstraction level, in addition to the material specification on RTL abstraction level.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134482282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Computing symbolic transfer functions of CC-based circuits using Coates Flow-Graph 用科茨流程图计算cc电路的符号传递函数
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487579
M. Fakhfakh, M. Pierzchala
{"title":"Computing symbolic transfer functions of CC-based circuits using Coates Flow-Graph","authors":"M. Fakhfakh, M. Pierzchala","doi":"10.1109/DTIS.2010.5487579","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487579","url":null,"abstract":"This brief presents a method for computing symbolic transfer functions of analog circuits encompassing fully differential (FDCCII) and differential voltage (DVCC) current conveyors. This method is based on the Coates Flow-Graph. New flow-graph stamps for these elements are presented.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114091650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
OFDM modem design and implementation for narrowband Powerline communication 窄带电力线通信OFDM调制解调器的设计与实现
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487584
Souha Souissi, Arwa Ben Dhia, F. Tlili, C. Rebai
{"title":"OFDM modem design and implementation for narrowband Powerline communication","authors":"Souha Souissi, Arwa Ben Dhia, F. Tlili, C. Rebai","doi":"10.1109/DTIS.2010.5487584","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487584","url":null,"abstract":"Automatic meter reading (AMR) technology allows energy suppliers to exploit their own infrastructure to bill their customers in an efficient and economical way using Power Line Communications (PLC). At this moment, new applications and services are required by market such as load and alarm management, remote monitoring and disconnection, etc. Thus, narrowband PLC modems should satisfy these services, provide high throughput and keep a low cost. In this paper, we propose a design methodology of a narrowband OFDM based PLC modem, its implementation on embedded processor and optimization of three building blocks: FFT, Viterbi, and convolutional encoder.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"2676 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132573104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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