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5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2018-11-12 DOI: 10.7767/9783205200468.front
I. Voyiatzis
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引用次数: 0
RF MEMS fluidic variable inductor 射频MEMS流体可变电感器
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487544
I. El Gmati, R. Fulcrand, P. Calmon, A. Boukabache, P. Pons, H. Boussetta, A. Kallala, K. Besbes
{"title":"RF MEMS fluidic variable inductor","authors":"I. El Gmati, R. Fulcrand, P. Calmon, A. Boukabache, P. Pons, H. Boussetta, A. Kallala, K. Besbes","doi":"10.1109/DTIS.2010.5487544","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487544","url":null,"abstract":"This paper presents a continuously variable inductor for Radiofrequency applications. The inductor is built using lamination of photosensitive films process. The variation principle is based on the change area of the loop inductor. The fluid moves between inter-spires distance and shortening the path length of the current through the structure; leading to reduction of the stored magnetic energy, and hence the inductance. A detailed electrical analysis is conducted to predict the tuning range of the inductor using simulation tools such as HFSS. At 3 GHz, the simulated inductor is continuously varied from 7 nH to 2.98 nH, i.e., the variable range is above 100%. The fact that the device is fabricated on glass process enhances the potential for system integration. The proposed variable inductor is perspective key component for the multi-band RF circuits such as electrically controllable matching circuits and wide tuning range voltage controlled oscillator (VCO).","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Model checking optimization of safe Control Embedded Components with refinement 安全控制嵌入式元件的模型校核优化
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487548
Atef Gharbi, M. Khalgui, S. Ben Ahmed
{"title":"Model checking optimization of safe Control Embedded Components with refinement","authors":"Atef Gharbi, M. Khalgui, S. Ben Ahmed","doi":"10.1109/DTIS.2010.5487548","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487548","url":null,"abstract":"This paper deals with model checking optimization of Software Embedded Control Components by applying refinement. We introduce a Software Embedded Control Component as an event-triggered software unit composed of an interface for any external interactions and an implementation allowing control actions of physical processes. A control system is assumed to be a composition of components with precedence constraints to control the plant. To ensure safety, an intelligent software agent controls the plant and applies automatic reconfiguration whenever a physical error occurs in the plant. We propose in this paper to model checking these different reconfigurations through a refinement method realized step by step. The contributions of the paper are applied to two Benchmark Production Systems available in our research laboratory.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117172227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Verification of SystemC transaction level models using an aspect-oriented and generic approach 使用面向方面和通用方法验证SystemC事务级模型
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487605
Meriam Kallel, Younes Lahbib, R. Tourki, A. Baganne
{"title":"Verification of SystemC transaction level models using an aspect-oriented and generic approach","authors":"Meriam Kallel, Younes Lahbib, R. Tourki, A. Baganne","doi":"10.1109/DTIS.2010.5487605","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487605","url":null,"abstract":"Transaction level modeling (TLM) has become an accepted and well supported paradigm that is intended to create hardware designs at high abstraction levels. In this paper, we present a methodology that targets the verification of SystemC transaction level models using runtime monitoring. Aspect-oriented programming (AOP) techniques are exploited to handle the high-level TLM features in an automated and generic way. No modifications are needed in the design's SystemC code. In addition, a wide range of functional and performance assertions is addressed. We demonstrate the usefulness of our approach on a realistic system-on-chip platform based on TLM-2.0 standard compliant models and including Open Core Protocol (OCP) interfaces.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114939097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures 基于gals的MPSoC架构的全异步NoC中的能量/吞吐量权衡
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487580
A. Rahimi, M. Salehi, Saleh Mohammadi, S. M. Fakhraie, A. Azarpeyvand
{"title":"Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures","authors":"A. Rahimi, M. Salehi, Saleh Mohammadi, S. M. Fakhraie, A. Azarpeyvand","doi":"10.1109/DTIS.2010.5487580","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487580","url":null,"abstract":"In this paper we evaluate the compromising effect of energy saving and throughput degradation on a fully asynchronous NoC architecture with regards to the dynamic voltage scaling guidelines. The investigated fully asynchronous NoC architecture is suitable for GALS-based MPSoCs architectures. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations, where the energy/throughput trade-off is reported and analyzed. Our results indicate that, although lower power may also be achieved by dynamic throughput scaling, this technique yields negligible energy saving for our asynchronous NoC. Therefore, we suggest a dynamic voltage scaling for this architecture which can save 40% energy at the expense of 13% throughput degradation.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114414431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Evaluation of FIR filters implementations for low power multistandard receivers 低功耗多标准接收机FIR滤波器实现的评估
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487594
N. Khouja, K. Grati, A. Ghazel, B. Le Gal
{"title":"Evaluation of FIR filters implementations for low power multistandard receivers","authors":"N. Khouja, K. Grati, A. Ghazel, B. Le Gal","doi":"10.1109/DTIS.2010.5487594","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487594","url":null,"abstract":"The idea behind this work is to extract from a large number of FIR filter syntheses several curves that estimate the area and power consumption. The aim is to help filter designer to make the right choice regarding decimation factor versus area and power consumption. The performed experiences show that for a given filter order, the choice of the decimation factor has a deep impact on the area and power consumption.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122006496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A concurrent BIST architecture based on Monitoring Square Windows 一种基于监控广场窗口的并行BIST架构
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487561
I. Voyiatzis, T. Haniotakis, C. Efstathiou, H. Antonopoulou
{"title":"A concurrent BIST architecture based on Monitoring Square Windows","authors":"I. Voyiatzis, T. Haniotakis, C. Efstathiou, H. Antonopoulou","doi":"10.1109/DTIS.2010.5487561","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487561","url":null,"abstract":"Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in on-line and in off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel concurrent BIST scheme is presented, termed Square Windows Monitoring (SWiM) concurrent BIST, which is based on monitoring input vectors using a square window; it is shown that SWiM is superior to previously proposed input vector monitoring schemes, with respect to concurrent test latency and hardware overhead trade-off.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"407 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122196928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Comparing crossbar-based nano/CMOS architectures 比较基于交叉棒的纳米/CMOS架构
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487598
C. Teodorov
{"title":"Comparing crossbar-based nano/CMOS architectures","authors":"C. Teodorov","doi":"10.1109/DTIS.2010.5487598","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487598","url":null,"abstract":"During the last few years, a novel set of nanoscale technologies has emerged as an alternative to traditional CMOS circuits. They bring certain promises such as high-density, reduced manufacturing costs, but they also present some challenges. Trying to compare some of the proposed architectures we realized that it is impossible to objectively evaluate them, problem that hinder our ability to practically develop these architectures. To compare these architectures we extracted the similarities between these fabrics and based on these similarities we tried to match the results presented in the literature. Following this methodology we were unable to objectively compare these emergent architectures. In this paper we present the main reasons why such an evaluation is not practical and we show how a common vocabulary and design methodology can solve this problem.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129588702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Techniques for electromagnetic attacks enhancement 增强电磁攻击的技术
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487590
Youssef Souissi, J. Danger, S. Mekki, S. Guilley, Maxime Nassar
{"title":"Techniques for electromagnetic attacks enhancement","authors":"Youssef Souissi, J. Danger, S. Mekki, S. Guilley, Maxime Nassar","doi":"10.1109/DTIS.2010.5487590","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487590","url":null,"abstract":"Electromagnetic attacks (EMA) pose real threats to embedded devices containing a secret information. Such attacks are of great concern since they are completely passive, low cost and easily mounted in practice. In this paper, we propose two innovative techniques to enhance electromagnetic attacks by reducing the number of measurements needed to succeed an attack on cryptographic implementations. The first method is based on the electromagnetic shielding theory which aims at decreasing the contribution of external noise sources. Whereas, the second provides an algorithmic solution to preprocess electromagnetic signals using the Kalman filtering (KF).","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128314983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Using low frequency noise method to characterize an AlGaAs/GaAs high electron mobility heterostructure 利用低频噪声方法表征AlGaAs/GaAs高电子迁移率异质结构
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2010-03-23 DOI: 10.1109/DTIS.2010.5487567
S. Mouetsi, A. El Hdiy
{"title":"Using low frequency noise method to characterize an AlGaAs/GaAs high electron mobility heterostructure","authors":"S. Mouetsi, A. El Hdiy","doi":"10.1109/DTIS.2010.5487567","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487567","url":null,"abstract":"The low frequency noise (LFN) method was used to characterize a two-dimensional electron gas (2DEG) in a double AlGaAs/GaAs/AlGaAs heterojunction from room temperature to cryogenic one. Measurements on noise presented by the power spectral density (PSD) of drain voltage are analyzed as a function for different applied voltages and temperatures in the frequency range from 1 Hz to 100 kHz. PSD can be considered as a sum of different contributions (thermal noise, generation- recombination noise and 1/f noise). The experimental results of the thermal noise versus device length of the sample permitted us to estimate the contribution of the contact noise and the results showed the good quality of contacts. The generation recombination noise is studied and traps responsible for capture and emission of carriers are identified by their activation energy and capture cross-section.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127969118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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