A concurrent BIST architecture based on Monitoring Square Windows

Abstract

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in on-line and in off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel concurrent BIST scheme is presented, termed Square Windows Monitoring (SWiM) concurrent BIST, which is based on monitoring input vectors using a square window; it is shown that SWiM is superior to previously proposed input vector monitoring schemes, with respect to concurrent test latency and hardware overhead trade-off.