{"title":"A new PSO-based approach to study the nanoscale DG MOSFETs","authors":"T. Bendib, F. Djeffal, M. Abdi","doi":"10.1109/DTIS.2010.5487571","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487571","url":null,"abstract":"The Double Gate (DG) MOSFET has been proposed as potential alternative to the conventional bulk CMOS structure for extended CMOS scalability beyond 30 nm partly due to its immunity to short channel effects. So, the objective of this work is to provide an accurate drain current model based on an automatic parameter extraction method with PSO (Particle Swarm Optimization) for Current-Voltage-based MOSFET models. Extracted parameter values reproduce I–V characteristics within 5% RMS error for wide range of gate lengths. It is shown that the I–V characteristics predicted by our analytical model are in close agreement with 2-D numerical simulation results.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128029376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power architecture of motion estimation and efficient intra prediction based on hardware design for H.264","authors":"H. Chaouch, S. Dhahri, A. Zitouni, R. Tourki","doi":"10.1109/DTIS.2010.5487604","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487604","url":null,"abstract":"The coding gains of the H.264/AVC video encoder, come from the improvement of the prediction method for intra and inter prediction in goal to achieve best image quality. However, their enormous computation, high complexity and the dissipated power are the main penalties. The approach proposed in this paper invests and exploits the best hardware solution for intra and inter prediction. Intra prediction is based on nine luma modes by using a 4×4 block for predicted MB (macro-block). Inter prediction is based on a novel low power Hardware Adaptive Motion Estimator (HAME), which is essential for the portable systems that integrate the Full Search (FS), the Gradient Search (GS) and the Four Step Search (FSS) algorithms. Our aim is to achieve an acceptable image quality with the reduction of the computational cost by using hardware accelerator. All modules were designed by using Very High Speed Integrated Circuit (VHSIC) and operate with about 350 MHz clock frequency for inter and intra prediction. The Synopsys environments are used and are based on CMOS 45 nm ASIC technology.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134434417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Non Volatile Memory signatures extraction for defects diagnosis purpose","authors":"H. Aziza, J. Plantier, J. Portal","doi":"10.1109/DTIS.2010.5487556","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487556","url":null,"abstract":"The purpose of this paper is to present Non Volatile Memories analog signatures extraction. This work focuses on Flash and EEPROM memories. Analog signatures can be specific voltage or current values representative of the memory cell behavior. These signatures can be used to give a visual indication of relative cell signatures of a whole memory matrix. A spatial distribution of analog signatures is proposed as a 2D and 3D bitmap. Thanks to this new approach, it is possible to investigate more finely the change of memory array signature distributions during write/erase cycles and to diagnosis memory defects. Besides, the influence of peripheral circuits on memory cells behavior can be detected.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129239939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A mixed style architecture for low power multipliers based on a bypass technique","authors":"G. Economakos, D. Bekiaris, K. Pekmestzi","doi":"10.1109/DTIS.2010.5487585","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487585","url":null,"abstract":"In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption. While this idea offers great savings mainly to array multipliers, due to their regular interconnection scheme, the reduced area and fast speed of tree multipliers is a real temptation for the designer. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that the bypass technique offers minimum power consumption for all cases while the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124223903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Si-Yu Liao, M. Najari, C. Maneux, S. Frégonèse, T. Zimmer, H. Mnif, N. Masmoudi
{"title":"Optically-Gated CNTFET compact model including source and drain Schottky barrier","authors":"Si-Yu Liao, M. Najari, C. Maneux, S. Frégonèse, T. Zimmer, H. Mnif, N. Masmoudi","doi":"10.1109/DTIS.2010.5487554","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487554","url":null,"abstract":"Nanoelectronic circuit design flow is based on device description through the compact models available in the designer device library. We have developed a compact model for the Optically-Gated CNTFET by investigating the trapping-detrapping of electron effects in the device. This compact model represents an important enhancement of conventional CNTFET models already released. Especially, it includes the optical writing, the electrical reset, and the non-volatile memory effect of the device operations. Moreover, it describes also the influence of the device performances of the Schottky barrier metal-CNT contact at the source and drain side. We also demonstrate that the simulation results obtained using this compact model, are in close agreement with preliminary experimental measurements. Furthermore, transient simulations predict the Schottky barrier impact on the memory operation.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123434030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance of low-pass filter based on non-uniform capacitor sections","authors":"I. Oueriemi, F. Choubani, I. Huynen, J. Raskin","doi":"10.1109/DTIS.2010.5487587","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487587","url":null,"abstract":"This paper presents a new design of stepped-impedance low-pass filter in microstrip technology based on the use of non-uniform sections. The simulated results show significant performance improvement as steeper slope and better harmonic suppression. This type of non-uniform low pass filter is moreover more compact than its conventional counterpart.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120980170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Neuro-inspired learning of low-level image processing tasks for implementation based on nano-devices","authors":"O. Brousse, M. Paindavoine, C. Gamrat","doi":"10.1109/DTIS.2010.5487553","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487553","url":null,"abstract":"As nanoscale devices such as OG-CNTFETs are under studies and may be used in a near futur, we choose to investigate in wich application domain such components may be of the most interest. In this paper we present how neural networks can be used to implement functions on nano-scale components. This method has been tested in the image processing application field.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134358007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling SW to HW task migration for MPSOC performance analysis","authors":"I. Bennour, D. Sebai, A. Jemai","doi":"10.1109/DTIS.2010.5487581","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487581","url":null,"abstract":"Codesign choices of a system differ in terms of different hardware/software partitions, different types of architectural components, different communication architectures, etc. This paper presents an analytic method to estimate the gain on a system throughput when a software task is selected to be moved to hardware during the codesign process. The method is based on formal transformations of a Synchronous Data Flow Graph that models the application as well as its mapping to architecture. The proposed method is applied to the MJPEG decoder using the predictable MPSOC design tool SDF3 [2].","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121713938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Maalej, M. Ben-Romdhane, P. Desgreys, P. Loumeau, C. Rebai, A. Ghazel
{"title":"Data acquisition test platform for non uniformly controlled ADC","authors":"A. Maalej, M. Ben-Romdhane, P. Desgreys, P. Loumeau, C. Rebai, A. Ghazel","doi":"10.1109/DTIS.2010.5487563","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487563","url":null,"abstract":"Non Uniform Sampling (NUS) was presented as an emerging solution to reduce aliases for ADC (Analog-to-Digital Converter) in Software Defined Radio receiver. In this paper, practical implementations of NUS, called TQ-RS (Time Quantized Random Sampling) are presented. A test setup for non uniformly controlled data acquisition system is detailed. Experimental results are presented and discussed.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124989378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A real-time FPGA-based implementation of target detection technique in non homogenous environment","authors":"R. Djemal","doi":"10.1109/DTIS.2010.5487550","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487550","url":null,"abstract":"This paper presents a high speed real-time target detection system for non homogenous environment based on FPGA Technology. The system implements a Backward Automatic Censored Ordered Statistics Detector (B-ACOSD) to maintain a Constant False Alarm Rate (CFAR) for Radar system with a time constraints in term of signal computing and target identification. The design flow and the hardware implementation of each module are introduced in detail. The proposed system can operate up to 115 MHz by using full pipeline organization and parallel computing which increase the speed up of the target detection system to satisfy the real-time constraints. The proposed architecture is designed, implemented, and tested using Stratix II EP2S60F672C3N FPGA Board. The system has the advantages of being simple, fast, and flexible with low development cost for a reference window of length 16 cells.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}