Low power architecture of motion estimation and efficient intra prediction based on hardware design for H.264

Abstract

The coding gains of the H.264/AVC video encoder, come from the improvement of the prediction method for intra and inter prediction in goal to achieve best image quality. However, their enormous computation, high complexity and the dissipated power are the main penalties. The approach proposed in this paper invests and exploits the best hardware solution for intra and inter prediction. Intra prediction is based on nine luma modes by using a 4×4 block for predicted MB (macro-block). Inter prediction is based on a novel low power Hardware Adaptive Motion Estimator (HAME), which is essential for the portable systems that integrate the Full Search (FS), the Gradient Search (GS) and the Four Step Search (FSS) algorithms. Our aim is to achieve an acceptable image quality with the reduction of the computational cost by using hardware accelerator. All modules were designed by using Very High Speed Integrated Circuit (VHSIC) and operate with about 350 MHz clock frequency for inter and intra prediction. The Synopsys environments are used and are based on CMOS 45 nm ASIC technology.