Modeling SW to HW task migration for MPSOC performance analysis

Abstract

Codesign choices of a system differ in terms of different hardware/software partitions, different types of architectural components, different communication architectures, etc. This paper presents an analytic method to estimate the gain on a system throughput when a software task is selected to be moved to hardware during the codesign process. The method is based on formal transformations of a Synchronous Data Flow Graph that models the application as well as its mapping to architecture. The proposed method is applied to the MJPEG decoder using the predictable MPSOC design tool SDF3 [2].