A mixed style architecture for low power multipliers based on a bypass technique

Abstract

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption. While this idea offers great savings mainly to array multipliers, due to their regular interconnection scheme, the reduced area and fast speed of tree multipliers is a real temptation for the designer. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that the bypass technique offers minimum power consumption for all cases while the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures.