A. Boudabous, A. Ben Atitallah, L. Khriji, P. Kadionik, N. Masmoudi
{"title":"FPGA implementation of vector directional distance filter","authors":"A. Boudabous, A. Ben Atitallah, L. Khriji, P. Kadionik, N. Masmoudi","doi":"10.1109/DTIS.2010.5487600","DOIUrl":null,"url":null,"abstract":"In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best execution time. After validation, using NiosII development board, we demonstrate a clearly improvement in the filtering speed compared to the software solution. Experiments on a large and diverse image sets show that our implementation approach achieves an excellent balance between simplicity, accuracy, and computational speed.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2010.5487600","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best execution time. After validation, using NiosII development board, we demonstrate a clearly improvement in the filtering speed compared to the software solution. Experiments on a large and diverse image sets show that our implementation approach achieves an excellent balance between simplicity, accuracy, and computational speed.