{"title":"神经横杆的高容错性","authors":"Djaafar Chabi, Jacques-Olivier Klein","doi":"10.1109/DTIS.2010.5487552","DOIUrl":null,"url":null,"abstract":"Proposed nanometer-scale electronic devices are generally expected to feature an increased probability of manufacturing defects. We present in this paper a novel, highly fault-tolerant architecture, based on memristor crossbar architecture that may enable reliable implementation of neural network. Simulation results of our learning method inspired of Delta rule [1] for monolayer crossbar, exhibits very fast convergence rate to learn Boolean functions. In addition we simulate the impact of defects to measure the ability of our architecture to repair defective neurons, using a competitive learning scheme with or without redundancy. The architecture is able to learn the Boolean functions with manufacturing defect rate up to 13% with reasonable redundancy amount. It shows the best fault-tolerance performance comparing with the other techniques like RMR, von Neumann multiplexing and reconfiguration.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Hight fault tolerance in neural crossbar\",\"authors\":\"Djaafar Chabi, Jacques-Olivier Klein\",\"doi\":\"10.1109/DTIS.2010.5487552\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Proposed nanometer-scale electronic devices are generally expected to feature an increased probability of manufacturing defects. We present in this paper a novel, highly fault-tolerant architecture, based on memristor crossbar architecture that may enable reliable implementation of neural network. Simulation results of our learning method inspired of Delta rule [1] for monolayer crossbar, exhibits very fast convergence rate to learn Boolean functions. In addition we simulate the impact of defects to measure the ability of our architecture to repair defective neurons, using a competitive learning scheme with or without redundancy. The architecture is able to learn the Boolean functions with manufacturing defect rate up to 13% with reasonable redundancy amount. It shows the best fault-tolerance performance comparing with the other techniques like RMR, von Neumann multiplexing and reconfiguration.\",\"PeriodicalId\":423978,\"journal\":{\"name\":\"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2010.5487552\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2010.5487552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Proposed nanometer-scale electronic devices are generally expected to feature an increased probability of manufacturing defects. We present in this paper a novel, highly fault-tolerant architecture, based on memristor crossbar architecture that may enable reliable implementation of neural network. Simulation results of our learning method inspired of Delta rule [1] for monolayer crossbar, exhibits very fast convergence rate to learn Boolean functions. In addition we simulate the impact of defects to measure the ability of our architecture to repair defective neurons, using a competitive learning scheme with or without redundancy. The architecture is able to learn the Boolean functions with manufacturing defect rate up to 13% with reasonable redundancy amount. It shows the best fault-tolerance performance comparing with the other techniques like RMR, von Neumann multiplexing and reconfiguration.