1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

{"title":"An analog-to-digital converter using charge-transfer technology","authors":"C. Eichelberger, W. Butler","doi":"10.1109/ISSCC.1977.1155694","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155694","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"93 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126199142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance, MOS EPROMs using a stacked-gate cell","authors":"P. Salsbury, W. Morgan, G. Perlegos, R. Simko","doi":"10.1109/ISSCC.1977.1155707","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155707","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131058316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automotive electronics: Going LSI?","authors":"M. Hoover","doi":"10.1109/ISSCC.1977.1155736","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155736","url":null,"abstract":"The advent of more complex automotive electronics systems is a stimulus to employ ICs of LSI complexity. As a corollary, complexity tends to intensify controversies over the details of the design considerations pertinent to LSI circuits. Following is a synopsis of three typical considerations subject to controversy: ( 1 centralization yes or no, (2) on-the-shelf versus custom components, (3) controlsystem design philosophy.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131308720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 16K × 1 bit dynamic RAM","authors":"P. Schroeder, R. Proebsting","doi":"10.1109/ISSCC.1977.1155625","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155625","url":null,"abstract":".4 16K x 1. BIT dynamic RAM capable o f 130-ns access time has bcen developed using a two-level N-channel polysilicon gate process and a single transistor cell. Utilizing the standard 16-pin package configuration, seven address bits are multiplexed. All clocks and othcr inputs are TTI. compatible. Maximum user flexibility has hecn provided by incorporating ___ 2 10% supplies, a nonlatched tri-state data output controlled by CAS, a+ multiplex timing window, page mode capability, and RAS-only refresh. A block diagram o f thc circuit is shown in Figure 1 and a photograph o f a fabricated device appears in Figure 2. The chip is organixcd internallyas a single 128 x 128 balanced array with both column dwodcrs and sense amplifiws located in a row through the center of the array. To maintain a balanced confiqration, each column decode circuit is divided into two parts with one hall on either side of the sense amplifiers. These column dccoders provide 1 of 64 selection. The final 1 of 128 column decoding -is accomplished by selection of one of two ' pairs o f data. data buses which also run through the center, and which are used for IjO coupling to the selected digit circuits. Since acccss is providcd to both the true and complement sense lines associated with each amplifier, no digit pullup transistors are requircd. This permits completely dynamic flipflop type detectors to be uscd, resulting in very low power consumption.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1952 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129371267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Poly I2L - A high-speed linear compatible structure","authors":"R. Davies, J. Meindl","doi":"10.1109/isscc.1977.1155731","DOIUrl":"https://doi.org/10.1109/isscc.1977.1155731","url":null,"abstract":"THE RELATIVELY SLOW SWITCHING speed of 12L fabricated using standard processes for linear integrated circuits limits opportunities for realizing complex, high quality, analog and digital functions on a single monolithic chip. This paper will present a new approach to increase significantly 12L speed ( < l o ns @ 100 pW/gatc), while retaining isolated 15-30 V NPN transistors on 5 G! em epitaxy, without increasing the complexity of the standard linear integrated circuit process.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129798265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Circuit device interface techniques for a 5-W 5-GHz bipolar microwave power transistor","authors":"G. Schreyer","doi":"10.1109/ISSCC.1977.1155710","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155710","url":null,"abstract":"THE USE of state-of-the-art circuit device interface techniques has made it possible to design a 5-W/5-GHz bipolar microwave power transistor: Figure 1. The device uses internal input and output matching circuits to combine the output power of six separate transistor cells. The transistor cell is a silicon bipolar device of an interdigitated structure employing refractory gold metalization, diffused emitter ballast resistors, an ion-implanted base, and a diffused phosphorus emitter. The most significant circuit technique used was to return the collector shunt inductor directly to the base bonding pad so that the reactive part of the output current does not flow in the common-mode inductance of the common base device; Figures 2 and 3. This reduction of current in the common-mode inductance reduces the detrimental effects of that parasitic element, allowing increased gain and stability. Gain and stability are also enhanced by the direct reduction of the common-mode inductance by double-bonding and by VZA holes through the Be0 substrate to return the base more directly to ground. The blocking capacitor for the collector shunt inductor is placed as close as possible to the transistor chips. Minimum distance between the transistor and the capacitor provides maximum real part transformation of the collector load impedance which reduces the VSWR that the remainder of the collector circuit must tune out and tends to reduce losses in the collector circuit. Also, the collector matching network is included entirely on the substrate to allow minimum VSWR at the internal-to-external circuit interface, and therefore, reduced losses at that interface. The input circuit is a minimum loss low-pass network allowing maximum transfer of drive power, while still maintaining an acceptable input match. To minimize the overall thermal resistance of the device, the six transistor cells are mounted such that there is a large physical separation between them. This layout provides The device as presented is capable of 250-MHz of bandwidth with circuit optimization. Overall bandwidth of over 500-MHz should be achievable with proper circuit optimization. Possible applications for this device or similar multicell devices are in transmitter amplifiers for troposcatter or satellite communications systems, phased-array radars, or as power oscillators for fuses or radar altimeters.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133727865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A stabilized, low-noise GaAs FET integrated oscillator with a dielectric resonator at C-band","authors":"H. Abe, Y. Takayama, A. Higashisaka, H. Takamizawa","doi":"10.1109/ISSCC.1977.1155711","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155711","url":null,"abstract":"TO USE G a h FET oscillators as power source in microwave communication systems, good temperature frequency-stability and low noise characteristic are essential’. A GaAs FET integrated oscillator stabilized with a high-Q dielectric resonator has been found to provide a highly-frequencystabilized, low-noise, compact RF power source. To realize optimal coupling between the oscillator and stabilizing resonant circuits, a large-signal design study was undertaken involving the measurement of the dynamic properties of the oscillator and resonant circuit. A stabilized oscillator output of 1OOmW with 17% efficiency and frequency temperature coefficient as low as 2.3 ppm/OC was obtained at 6-HGz. The FM noise characteristic has been improved more than 30dB by introducing the dielectric resonator. A common-source GaAs FET oscillator affords improved microwave performance through the optimization of the external feedback network. An unstabilized oscillator, with a series connection of microstrip lines and a dielectric capacitor as a feedback network2 generates 400-mW of microwave power with 38% efficiency at 6000MHq which is comparable to the maximum added power for an amplifier using an FET chip obtained from the same wafer.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127171729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of short and narrow channel effects for CAD-IGFET model","authors":"H. Kotecha, F. De La Moneda, K. Beilstein","doi":"10.1109/ISSCC.1977.1155682","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155682","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115431633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 16-bit monolithic I3L processor","authors":"C. Erickson, H. Hingarh, R. Moeckel, D. Wilnai","doi":"10.1109/ISSCC.1977.1155638","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155638","url":null,"abstract":"A SINGLE-CHIP 16-BIT MICROPROCESSOR with fixed point arithmetic using 2’s complement notation will be described. It executes the same instruction set as the NOVA line of minicomputers and has comparable performance and is packaged in a 40-pin DIP. Figure 1 is the logic symbol of the processor and shows various data and control lines noted below. (1)lnformation Bus IBo-IB15 is a 16-bit bidirectional 3-state bus used to transfer address, data, and instruction information between the processor and main memory, and to transfer data to and from I/O devices. (2)S ta tus Lines RUN, CARRY and INT.ON are used to convey the status information of the processor mainly for display on an operator console. (3) Operator Console Control Co-C3, RESET. Operator can control the operation of the processor by means of 4 coded lines (Co-3) and a RESET line. (4)lnput/Output Control 00.01, INT. REQ., DCH. REQ. Processor controls 1/0 devices by means of two coded control lines (00,Ol)I/O devices can interrupt the normal program flow by activating the INT. REQ. line and they can gain direct access to main memory bv activating the DCII. REQ. line. (5)!kmory Control Mo-M~, MBSY. Processor controls thc main memory by means o f 3 open collcctor control lines (Mo, M1, M2). It synchronizes itself to the memory cycle time indicated by the MBSY signal. ( 6 ) Timing SYN, CP, XTL, CIKOUT. Processor can operate with an on-chip oscillator when a crystal is tied between (CP) and (XTL,) or i t can operatc from an external clock (CP). Processor generates a synchronization signal (SYN) for all external devices. The internal clock is available to the outside world on (CLKOUT).","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114579298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bimodal MOS-bipolar monolithic kitchip array","authors":"S. Combs, J. Meindl","doi":"10.1109/ISSCC.1977.1155745","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155745","url":null,"abstract":"COMBINED FET/BJT TECHNOLOGIES have recently generated increasing interest’ 5’. This paper will describe fully complementary, combined MOS-bipolar technology optimized for use in a monolithic Kitchip array of unconnected transistors, resistors, and MOS capacitors. The need for high performance integrated circuits is often overriden by their development cost and poor potential for volume production. The Kitchip represents a quick, cost-effective means for bringing IC technology to many of these applications. Prefabricated Kitchip ICs may be transformed into virtually any simple digital or linear circuit configuration by using a single customizing aluminum interconnect pattern. The underlying eight masks defining the Kitchip are never altered. Several key features distinguish the Kitchip from available IC arrays. A new process yields two self-aligned, low current optimized bimodal (MOS or bipolar) N and P type transistors, low on-resistance VMOS switches for signal multiplexing, ion-implanted low and high value resistors, and a low voltage JFET. The operational mode of any bimodal transistor is determined only by the metal interconnection pattern. Therefore, micropower CMOS and complementary bipolar logic can be realized simultaneously with high performance MOS or bipolar linear functions on the same chip. Surface aluminum, polysilicon cross-unders, and diffused tunnels provide three levels of interconnection permitting efficient device utilization. Compared to a standard six mask linear process, fabrication of the Kitchip requires an additional ion-implant, polysilicon deposition and an anisotropic etch. The dual N type bimodal transistor, Figure 1, o erates as either a bipolar NPN or aluminum. gate VMOS transistor . The bimodal transistor features an isolated source and buried layer drain VMOS with channel characteristics determined by a boron (P-) ion implantation and conventional downward diffusion. Additional arsenic (N’) and boron (P’) implants precisely define its NPN beta, fT, and breakdown voltage.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128488562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}