{"title":"5w 5ghz双极微波功率晶体管的电路器件接口技术","authors":"G. Schreyer","doi":"10.1109/ISSCC.1977.1155710","DOIUrl":null,"url":null,"abstract":"THE USE of state-of-the-art circuit device interface techniques has made it possible to design a 5-W/5-GHz bipolar microwave power transistor: Figure 1. The device uses internal input and output matching circuits to combine the output power of six separate transistor cells. The transistor cell is a silicon bipolar device of an interdigitated structure employing refractory gold metalization, diffused emitter ballast resistors, an ion-implanted base, and a diffused phosphorus emitter. The most significant circuit technique used was to return the collector shunt inductor directly to the base bonding pad so that the reactive part of the output current does not flow in the common-mode inductance of the common base device; Figures 2 and 3. This reduction of current in the common-mode inductance reduces the detrimental effects of that parasitic element, allowing increased gain and stability. Gain and stability are also enhanced by the direct reduction of the common-mode inductance by double-bonding and by VZA holes through the Be0 substrate to return the base more directly to ground. The blocking capacitor for the collector shunt inductor is placed as close as possible to the transistor chips. Minimum distance between the transistor and the capacitor provides maximum real part transformation of the collector load impedance which reduces the VSWR that the remainder of the collector circuit must tune out and tends to reduce losses in the collector circuit. Also, the collector matching network is included entirely on the substrate to allow minimum VSWR at the internal-to-external circuit interface, and therefore, reduced losses at that interface. The input circuit is a minimum loss low-pass network allowing maximum transfer of drive power, while still maintaining an acceptable input match. To minimize the overall thermal resistance of the device, the six transistor cells are mounted such that there is a large physical separation between them. This layout provides The device as presented is capable of 250-MHz of bandwidth with circuit optimization. Overall bandwidth of over 500-MHz should be achievable with proper circuit optimization. Possible applications for this device or similar multicell devices are in transmitter amplifiers for troposcatter or satellite communications systems, phased-array radars, or as power oscillators for fuses or radar altimeters.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Circuit device interface techniques for a 5-W 5-GHz bipolar microwave power transistor\",\"authors\":\"G. Schreyer\",\"doi\":\"10.1109/ISSCC.1977.1155710\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"THE USE of state-of-the-art circuit device interface techniques has made it possible to design a 5-W/5-GHz bipolar microwave power transistor: Figure 1. The device uses internal input and output matching circuits to combine the output power of six separate transistor cells. The transistor cell is a silicon bipolar device of an interdigitated structure employing refractory gold metalization, diffused emitter ballast resistors, an ion-implanted base, and a diffused phosphorus emitter. The most significant circuit technique used was to return the collector shunt inductor directly to the base bonding pad so that the reactive part of the output current does not flow in the common-mode inductance of the common base device; Figures 2 and 3. This reduction of current in the common-mode inductance reduces the detrimental effects of that parasitic element, allowing increased gain and stability. Gain and stability are also enhanced by the direct reduction of the common-mode inductance by double-bonding and by VZA holes through the Be0 substrate to return the base more directly to ground. The blocking capacitor for the collector shunt inductor is placed as close as possible to the transistor chips. Minimum distance between the transistor and the capacitor provides maximum real part transformation of the collector load impedance which reduces the VSWR that the remainder of the collector circuit must tune out and tends to reduce losses in the collector circuit. Also, the collector matching network is included entirely on the substrate to allow minimum VSWR at the internal-to-external circuit interface, and therefore, reduced losses at that interface. The input circuit is a minimum loss low-pass network allowing maximum transfer of drive power, while still maintaining an acceptable input match. To minimize the overall thermal resistance of the device, the six transistor cells are mounted such that there is a large physical separation between them. This layout provides The device as presented is capable of 250-MHz of bandwidth with circuit optimization. Overall bandwidth of over 500-MHz should be achievable with proper circuit optimization. Possible applications for this device or similar multicell devices are in transmitter amplifiers for troposcatter or satellite communications systems, phased-array radars, or as power oscillators for fuses or radar altimeters.\",\"PeriodicalId\":416313,\"journal\":{\"name\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1977.1155710\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1977.1155710","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Circuit device interface techniques for a 5-W 5-GHz bipolar microwave power transistor
THE USE of state-of-the-art circuit device interface techniques has made it possible to design a 5-W/5-GHz bipolar microwave power transistor: Figure 1. The device uses internal input and output matching circuits to combine the output power of six separate transistor cells. The transistor cell is a silicon bipolar device of an interdigitated structure employing refractory gold metalization, diffused emitter ballast resistors, an ion-implanted base, and a diffused phosphorus emitter. The most significant circuit technique used was to return the collector shunt inductor directly to the base bonding pad so that the reactive part of the output current does not flow in the common-mode inductance of the common base device; Figures 2 and 3. This reduction of current in the common-mode inductance reduces the detrimental effects of that parasitic element, allowing increased gain and stability. Gain and stability are also enhanced by the direct reduction of the common-mode inductance by double-bonding and by VZA holes through the Be0 substrate to return the base more directly to ground. The blocking capacitor for the collector shunt inductor is placed as close as possible to the transistor chips. Minimum distance between the transistor and the capacitor provides maximum real part transformation of the collector load impedance which reduces the VSWR that the remainder of the collector circuit must tune out and tends to reduce losses in the collector circuit. Also, the collector matching network is included entirely on the substrate to allow minimum VSWR at the internal-to-external circuit interface, and therefore, reduced losses at that interface. The input circuit is a minimum loss low-pass network allowing maximum transfer of drive power, while still maintaining an acceptable input match. To minimize the overall thermal resistance of the device, the six transistor cells are mounted such that there is a large physical separation between them. This layout provides The device as presented is capable of 250-MHz of bandwidth with circuit optimization. Overall bandwidth of over 500-MHz should be achievable with proper circuit optimization. Possible applications for this device or similar multicell devices are in transmitter amplifiers for troposcatter or satellite communications systems, phased-array radars, or as power oscillators for fuses or radar altimeters.