1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

{"title":"A long pulse IMPATT amplifier for KU-band","authors":"S. Gray","doi":"10.1109/ISSCC.1977.1155737","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155737","url":null,"abstract":"WHEN ACTIVE RADARS arc used as seekers in guided missiles, they typically require peak transmitter output power in kilowatts to achieve ranges of several kilometers. When solidstate implementation is also required, one approach is to transmit long, medium power pulses and to use pulse compression in the radar receiver to achieve high effective peak power. A recent application of this nature resulted in al7-GHz IMPATT power amplifier which will be described in this paper. The design called for an unconditionally-stable, pulsed amplifier providing 20-dB gain at an output level of 1 0 W. Pulsewidths of 1 0 ps, a 10% duty cycle, and a 500-MHz bandwidth were also required.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128837131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An algorithmic analog-to-digital converter","authors":"R. McCharles, V. Saletore, W. Black, D. Hodges","doi":"10.1109/ISSCC.1977.1155701","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155701","url":null,"abstract":"ANALOG TO DIGITAL CONVERTERS perform digital logic, analog comparison and analog arithmetic. While digital logic and analog comparison are readily performed in LSI form, analog arithmetic has been largely excluded. For this reason, most single chip A/D converters use counting algorithms (such as dual slope) which are slow but which require only modest analog capability. .4 cyclic A/D converter’ can provide both a means of implcmenting successive approximation A/D converters and a means of performing general purpose analog arithmetic. This type of converter is ideal for realization using precision-ratioed capacitors A prototy e circuit using an analog CMOS process has been fabricated . The circuit features A/D conversion rates of 5 ps per bit, infinite resolution, 10 bits accuracy, and programmability, on a 3200 square mil die area. A simplified schematic of the A/D converter is shown in Figure 1. Two amplifiers, five ratio-matched capacitors ( 5 1 C ~ ) and two switches form a recirculating analog shift register wlth a gain of two. Three switches permit loading the register with an analog input and adding or subtracting the reference. A comparator to test the sign of output V, completes the circuit. A timing diagram showing the circuit in operation is shown in Figure 2. To start conversion the register is cleared by bringing both V1 and V2 high while the input is sampled by connecting C1 to Vin. This forces both V, and Yy to zero. During the second half of the initial cycle, C1 is connected t9 the analog ground and VI is brought low. This causes a charge of Cl*VIN to flow from C1 to C2. Since C1 and C2 are equal in value this will cause V, to be equal to the sampled value of VIN, and the comparator will indicate the sign of the sampled voltage. To determine the next bit V2 is brought low and VI is raised, while C1 is connected to ground (if the sign was positive) or to VREF (if the sign was negative). This causes the voltage Vx to be transferred to Vy, while 17, is forced to zero. At this point the charge in C1 is k CL*VREF, and the charge in Cg is C~*VIN. 2","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117060491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low end microprocessors: Will there be an industry standard?","authors":"W. Lattin","doi":"10.1109/ISSCC.1977.1155732","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155732","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121559629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low cost electronic serial memories","authors":"D. Buss, L. Terman","doi":"10.1109/ISSCC.1977.1155738","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155738","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Normally-off type GaAs MESFET for low power, high speed logic circuits","authors":"H. Ishikawa, H. Kusakawa, K. Suyama, M. Fukuta","doi":"10.1109/ISSCC.1977.1155642","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155642","url":null,"abstract":"wave amplifiers, but for high speed switching circuits’. Some of the logic using normally-on type GaAs MESFETs have large power dissipation and complicated circuit construction. The normally-off type GaAs MESFET logic has not as yet been reported, even though it is expected to have some attractive features such as low power dissipation and simple circuit configuration. Figure 1 is a microphotograph of the buffered output 13-stage ring oscillator consisting of normally-off type GaAs MESFETs and epitaxial resistors. A cutaway view of the inverter used in the ring oscillator is shown in Figure 2. The devices were fabricated on a sulfur-doped N-type epitaxial layer grown by VPE onto a semi-insulating Cr-doped substrate. The do ing density and thickness of the epitaxial layer was 1 x 101’cm-3 and 0.1 pm, respectively. The N-type layer outside the active area was etched down to the semiinsulating substrate to isolate inverters from each other. A dual-metal system was used. 0.04-pm thick Au-Ge eutectic alloy and 0.4-pm thick Au were continuously deposited as the first metal layer and were alloyed at 450’C for 120 seconds to make ohmic contact. Next, O.5pm-thick Si02 film which was used for the isolation of the dual metal layers was deposited by Chemical Vapor Deposition (CVD). This film was etched selectively to open the gate windows and the contact holes to the first metal layer. The second metal layer made with Cr-Pt-Au was used for the Schottky gate and crossing over or connecting to the GaAs MESFETs are substantially useful not only for micro-","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A monolithic IC for decibel-linear noise reduction","authors":"H. Yamada, M. Katakura","doi":"10.1109/ISSCC.1977.1155647","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155647","url":null,"abstract":"LEVEL COMPRESSION-EXPANSION systems (compandors), are widely used for reducing noise in signal transmission’ 3 2 . However, the IC realization of the log linear transformation system has been considered difficult due to the requirement for high performance PNP transistors in these circuits. A system which incorporates an equivalent PNP transistor with high performance characteristics will be described.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully ion implanted 4096-bit high speed DSA MOS RAM","authors":"K. Shimotori, K. Anami, Y. Nagayama, I. Okhura, M. Ohmori, T. Nakano, Y. Hayashi, Y. Tarui","doi":"10.1109/ISSCC.1977.1155678","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155678","url":null,"abstract":"DIFFUSION-SELF-ALIGNED (DM) M O S I C ~ ' , or D M O S ~ have received attention as subnanosecond and high density devices. In this paper, the experimental results of a DSA MOS memory fabricated by full ion implantation techniques to achieve better threshold voltage controllability will be dcscribed. Access time is 60 ns; power consumed is 950mW. Figure 1 shows cross section of the DSA E-D inverter. It is apparent from the figure, that the effective channel region of the DSA transistor is determined by the diffusion length difference between boron and arsenic layer. All dopants were deposited by ion implantatio-n method on P(71) Si substrate; resistivity was 100 \"200 Q-cm, crystal orientation (loo), respectively. The threshold voltage of the device was controlled within 1.20 ? 0.15V and the effective channel length was 0.4 pm. The gain factor was 5 times larger than that of the conventional NMOS3. Features of the DSA MOS process are: 1 ) E-D gate achieved by N-channel 71 planar technique; 2 ) selective oxidation process (SOP) adapted to obtain high packing density and to reduce surface steps; 3) Si gate also used for a smaller feedback capacitance and higher packing density; and 4) all dopants deposited by ion implantation method to improve control of threshold voltage. To evaluate the basic electrical characteristics of these devices, 1 9 stag: ring oscillators have been fabricated by varing process parameters. Figure 2 shows the propagation delay time versus power dissipation, where the parameters were varied for the amount of channel dope to the depletion FET and power supply voltages. In the unhatched region, the driving capability of the DSA MOS FET is smaller than that of the load FET, thus the inverter does not operate. The minimum power delay product (0.05 pJ) and the minimum propagation delay time (0.32 ns) are shown in the ploy. Using this process, a 4096-bit fully decoded dynamic R/W random access memory was developed (Figure 3) using a 5 p m minimum as a base. The memory cell uses a 1 Tr/cell structure to avoid Vth to minimize inverse connection effects due to high __","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120992882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Semiconductor RAMs: Limits to growth","authors":"L. Terman, W. Kosonocky","doi":"10.1109/ISSCC.1977.1155729","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155729","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115510271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sensing technique for self-contained charge-coupled split-electrode filters","authors":"C. Séquin, M. Tompsett, D. Sealer, P. Suciu, P. Ryan","doi":"10.1109/ISSCC.1977.1155718","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155718","url":null,"abstract":"A SELF-CONTAINED charge-coupled 55-tap split-electrode filter will be described in this paper. The major problem that had to be solved was that of transforming the signal from the sense electrodes into a usable output signal with a large dynamic range and a minimal harmonic distortion. The factors that must be considered in formulating a solution to this problem are: (1) eliminating the effects of depletion capacitance, (2) detecting a difference signal in the presence of a large common mode signal and (3) preventing reset noise in the detection circuitry. A practical method to avoid the effects of depletion capacitance under the split sense electrodes is to keep these electrodes at a fixed potential during the sensing process by using a feedback loop around an operational amplifier as indicated in Figure 1. This sensing circuitry is optimally used in conjunction with a voltage input to the charge transfer channel, where the charge packets are metered under an MOS electrode, (MW), the geometry of which is the same as that of the sense electrodes, and which is also kept at the same potential VSE; Figure 1. The overall transfer characteristic from the voltage applied to the input diode, (and thus the interface potential in the metering well MW) to the amount of image charge produced on the sense electrodes (and hence the output voltage V O ~ T ) can then be expected to be linear. Various possible ways to clamp the sense electrodes to a given potential and to extract the desired output signal have been discussed earlier’’2. A novel approach to extract this difference signal in the presence of the considerably larger common mode signal is shown in Figure 2. One amplifier (AD) performs the differencing operation, while the other amplifier ( Ac) is used to suppress the common mode signal on the two sense busses. AC operates by comparing the arithmetic mean of the sense electrode potentials to the sense voltage reference VSE and feeds back the same error signal to both sense busses through capacitors CCt and Cc. The feedback signal around AD through CDwll maintain the balance between the two sense busses, and the combined","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128684829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A monolithic companding D/A converter","authors":"J. Schoeff","doi":"10.1109/ISSCC.1977.1155668","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155668","url":null,"abstract":"COMPANDED PULSE CODE MODULATED (PCM) transmission of voice signals has become standardized through widespread use of the Bell system p-law and the CCITT** A-law transfer characteristics. Until now, all codecs (eoder/decoders) for these communication systems have been fabricated in either discrete or hybrid form and have been relatively expensive. This paper will present a newly developed monolithic digital-to-analog converter specifically designed for compression and expansion of signals according to the existing PCM standard. This converter, however, is not limited to PCM communication, but may be used in other areas such as data acquisition, servo controls, data recording, telemetry, voice synthesis, log attenuation, secure communications, sonar, and many other applications which require a 12-bit plus sign dynamic range and the convenience of an 8-bit digital code. When used in a telecommunications application, the companding DAC is a complete PCM decoder, with metal options for p-law and A-law. A one-half step decision level for encoding is provided within the circuit and controlled with the encode/decode logic input. This current offsets the entire transfer characteristic one half step, regardless of the value of the output current. The outputs are multiplexed for time sharing of one DAC for both encode and decode operation. The DAC settling time is 500 ns, and i t will decode more than 32 PCM channels in 125 ps, which is the sampling period at 8 kHz. In a shared encoder it will convert eight channels, assuming a 1 0 ps sample and hold acquisition time. The outputs are high impedance, high compliance current sources and will interface with most balanced loads. The reference inputs will accept a fixed reference or a positive or negative multiplying input. The transfer characteristic of the companding DAC is shown in Figure 1. The output consists of eight positive chords and eight negative chords, each containing sixteen steps. The slopes of these chords are binarily related with the chord at the origin having steps equivalent in size to those in a 12-bit converter. The step size is a nearly constant 3.2% of reading throughout most of the dynamic range, which corresponds to approximately 0.3 dB per step. Each successive chord endpoint is 6 dB below the next higher endpoint for every chord in the A-law specification, and follows this for most chords in the p-law. The dynamic range, or ratio, of the full scale to the smallest step size is 72 dB for the p-law version and 66 dB for the A-law unit. The electrical specifications for the circuit are summarized in Table I.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121733980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}