1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

{"title":"A long pulse IMPATT amplifier for KU-band","authors":"S. Gray","doi":"10.1109/ISSCC.1977.1155737","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155737","url":null,"abstract":"WHEN ACTIVE RADARS arc used as seekers in guided missiles, they typically require peak transmitter output power in kilowatts to achieve ranges of several kilometers. When solidstate implementation is also required, one approach is to transmit long, medium power pulses and to use pulse compression in the radar receiver to achieve high effective peak power. A recent application of this nature resulted in al7-GHz IMPATT power amplifier which will be described in this paper. The design called for an unconditionally-stable, pulsed amplifier providing 20-dB gain at an output level of 1 0 W. Pulsewidths of 1 0 ps, a 10% duty cycle, and a 500-MHz bandwidth were also required.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128837131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bimodal MOS-bipolar monolithic kitchip array","authors":"S. Combs, J. Meindl","doi":"10.1109/ISSCC.1977.1155745","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155745","url":null,"abstract":"COMBINED FET/BJT TECHNOLOGIES have recently generated increasing interest’ 5’. This paper will describe fully complementary, combined MOS-bipolar technology optimized for use in a monolithic Kitchip array of unconnected transistors, resistors, and MOS capacitors. The need for high performance integrated circuits is often overriden by their development cost and poor potential for volume production. The Kitchip represents a quick, cost-effective means for bringing IC technology to many of these applications. Prefabricated Kitchip ICs may be transformed into virtually any simple digital or linear circuit configuration by using a single customizing aluminum interconnect pattern. The underlying eight masks defining the Kitchip are never altered. Several key features distinguish the Kitchip from available IC arrays. A new process yields two self-aligned, low current optimized bimodal (MOS or bipolar) N and P type transistors, low on-resistance VMOS switches for signal multiplexing, ion-implanted low and high value resistors, and a low voltage JFET. The operational mode of any bimodal transistor is determined only by the metal interconnection pattern. Therefore, micropower CMOS and complementary bipolar logic can be realized simultaneously with high performance MOS or bipolar linear functions on the same chip. Surface aluminum, polysilicon cross-unders, and diffused tunnels provide three levels of interconnection permitting efficient device utilization. Compared to a standard six mask linear process, fabrication of the Kitchip requires an additional ion-implant, polysilicon deposition and an anisotropic etch. The dual N type bimodal transistor, Figure 1, o erates as either a bipolar NPN or aluminum. gate VMOS transistor . The bimodal transistor features an isolated source and buried layer drain VMOS with channel characteristics determined by a boron (P-) ion implantation and conventional downward diffusion. Additional arsenic (N’) and boron (P’) implants precisely define its NPN beta, fT, and breakdown voltage.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128488562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of short and narrow channel effects for CAD-IGFET model","authors":"H. Kotecha, F. De La Moneda, K. Beilstein","doi":"10.1109/ISSCC.1977.1155682","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155682","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115431633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A stabilized, low-noise GaAs FET integrated oscillator with a dielectric resonator at C-band","authors":"H. Abe, Y. Takayama, A. Higashisaka, H. Takamizawa","doi":"10.1109/ISSCC.1977.1155711","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155711","url":null,"abstract":"TO USE G a h FET oscillators as power source in microwave communication systems, good temperature frequency-stability and low noise characteristic are essential’. A GaAs FET integrated oscillator stabilized with a high-Q dielectric resonator has been found to provide a highly-frequencystabilized, low-noise, compact RF power source. To realize optimal coupling between the oscillator and stabilizing resonant circuits, a large-signal design study was undertaken involving the measurement of the dynamic properties of the oscillator and resonant circuit. A stabilized oscillator output of 1OOmW with 17% efficiency and frequency temperature coefficient as low as 2.3 ppm/OC was obtained at 6-HGz. The FM noise characteristic has been improved more than 30dB by introducing the dielectric resonator. A common-source GaAs FET oscillator affords improved microwave performance through the optimization of the external feedback network. An unstabilized oscillator, with a series connection of microstrip lines and a dielectric capacitor as a feedback network2 generates 400-mW of microwave power with 38% efficiency at 6000MHq which is comparable to the maximum added power for an amplifier using an FET chip obtained from the same wafer.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127171729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Normally-off type GaAs MESFET for low power, high speed logic circuits","authors":"H. Ishikawa, H. Kusakawa, K. Suyama, M. Fukuta","doi":"10.1109/ISSCC.1977.1155642","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155642","url":null,"abstract":"wave amplifiers, but for high speed switching circuits’. Some of the logic using normally-on type GaAs MESFETs have large power dissipation and complicated circuit construction. The normally-off type GaAs MESFET logic has not as yet been reported, even though it is expected to have some attractive features such as low power dissipation and simple circuit configuration. Figure 1 is a microphotograph of the buffered output 13-stage ring oscillator consisting of normally-off type GaAs MESFETs and epitaxial resistors. A cutaway view of the inverter used in the ring oscillator is shown in Figure 2. The devices were fabricated on a sulfur-doped N-type epitaxial layer grown by VPE onto a semi-insulating Cr-doped substrate. The do ing density and thickness of the epitaxial layer was 1 x 101’cm-3 and 0.1 pm, respectively. The N-type layer outside the active area was etched down to the semiinsulating substrate to isolate inverters from each other. A dual-metal system was used. 0.04-pm thick Au-Ge eutectic alloy and 0.4-pm thick Au were continuously deposited as the first metal layer and were alloyed at 450’C for 120 seconds to make ohmic contact. Next, O.5pm-thick Si02 film which was used for the isolation of the dual metal layers was deposited by Chemical Vapor Deposition (CVD). This film was etched selectively to open the gate windows and the contact holes to the first metal layer. The second metal layer made with Cr-Pt-Au was used for the Schottky gate and crossing over or connecting to the GaAs MESFETs are substantially useful not only for micro-","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wideband DC-coupled amp/schmidt","authors":"C. Shinn","doi":"10.1109/ISSCC.1977.1155669","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155669","url":null,"abstract":"AN ALL MONOLITHIC, dc to > I GI*, amplifier/Schmidt trigger with 8 mV rms input sensitivity has been designed using a junction-isolated 5 GHz fT process in spite of the inherent high capacitances. Included on a 1.39 x 1.59 mm chip are electronic gain control, 180’ phase switching, ECL line driver output, all biasing circuits and a one-shot LED driver. A functional block diagram is shown in Figure 1. The amplifier is composed of a cascade of three identical modified Gilbert gain cells’. The current gain of this type of circuit is set by the ratio of device input impedances which in turn are a function of their quiescent currents. Because the currents are added at the output of each stage, a cascade requires a geometric increase in the power dissipation for each additional stage. N t h even the first stage current constrained to be fairly high to obtain wide bandwidth, a cascade would be unreasonable. Modifying the gain cell by the addition of emitter resistors allows the input impedance and thus the current gain, to become independent of dc bias. Furthermore, this modification generally results in a substantial reduction in the mean squared output noise current (in2) since the expression is changed from:","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129876986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Aids to the layout of custom LSI","authors":"J. Heightley","doi":"10.1109/ISSCC.1977.1155734","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155734","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra high speed 1K-bit RAM with 7.5 ns access time","authors":"H. Mukai, K. Kawarada, K. Kondo, K. Toyoda","doi":"10.1109/ISSCC.1977.1155702","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155702","url":null,"abstract":"A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130349483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fast 1024-bit bipolar RAM using JFET load devices","authors":"M. Phan, J. Shier, A. Evans","doi":"10.1109/ISSCC.1977.1155633","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155633","url":null,"abstract":"IT HAS LONG BEEN recognized that the need for compact load devices is one of the main problems in building dense bipolar integrated circuits. In recent years several quite promising new approaches to this problem have been developed, including: (1) very high value P-type resistors made by ion implantation (2) the use of lateral PNP transistors to supply and limit the operating current ( 12L) and (3) various kinds of vacuumdeposited resistive materials. The JFET loads to be presented provide yet another way of achieving very compact load elements in bipolar integrated circuits. The JFET loads use the lightlydoped N-type channels which appear under the isolation oxide in an oxide-isolated structure employing an N-type epitaxial layer. These channels arise from the preferential segregation of the dopant during the growth of the isolation oxide’ and have been found to be stable and reproducible. The delineation of the load device is accomplished by a masked P type doping step made prior to epitaxial growth, with the P regions serving as channel stoppers between isolated devices. A load device is produced by simply omitting the channel stopper between two N regions to be connected to the load and thus is physically located in the isolation regions an aspect which substantially improves the circuit density by using space wasted in most bipolar structures; Figures 1 and 4. The load device is best described as a substrate-gate JFET (Figure 2) with many advantages: (1) it is very compact, equivalent resistances of 1 Mi?, being realized in 1 t o 2 mil2 area (including the channel stoppers), (2) i t behaves like a constant-current source, rather like the depletion loads u ed in MOS devices but without the need for gate metalization over it, (3) it connects readily to any part of a transistor collector region without the need for contacts or metalization, (4) its position under thick oxide minimizes parasitic capacitance and sensitivity to potentials of the overlying metalization, ( 5 ) the light doping level in substrate and load gives a low capacitance to substrate, and (6) the sheet resistance and nonlinear properties of these loads can be varied over a very broad range by adjusting process parameters. The process, which provides very shallow double-diffused NPN transistors with washed emitters, PtSi Schottky diodes, and high-beta vertical PNP transistors, lends itself particularly well to the use of a diode-coupled cell for the main storage flipflops in an all-TTL RAM design. As a result a 1024-bit TTL RAM was chosen for the initial design using the JFET load 1 Grove, A S . , Leistiko, 0. and Sah, C.T., “Redistribution of Acceptor and Donor Impurities During Thermal Oxidation of Silicon”, J. Applied Physics, Vol. 35, p. 2695; 1964. Lynes, D.J. and Hodges. D.A., “A Diode-Coupled Bipolar Transistor Memory Cell”, ISSCC Digest of Technical Papers, p. 44-45; Feb., 1970. 2 devices. These loads allowed the use of a compact, low-powerdissipation diode-coupled c","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128300408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sensing technique for self-contained charge-coupled split-electrode filters","authors":"C. Séquin, M. Tompsett, D. Sealer, P. Suciu, P. Ryan","doi":"10.1109/ISSCC.1977.1155718","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155718","url":null,"abstract":"A SELF-CONTAINED charge-coupled 55-tap split-electrode filter will be described in this paper. The major problem that had to be solved was that of transforming the signal from the sense electrodes into a usable output signal with a large dynamic range and a minimal harmonic distortion. The factors that must be considered in formulating a solution to this problem are: (1) eliminating the effects of depletion capacitance, (2) detecting a difference signal in the presence of a large common mode signal and (3) preventing reset noise in the detection circuitry. A practical method to avoid the effects of depletion capacitance under the split sense electrodes is to keep these electrodes at a fixed potential during the sensing process by using a feedback loop around an operational amplifier as indicated in Figure 1. This sensing circuitry is optimally used in conjunction with a voltage input to the charge transfer channel, where the charge packets are metered under an MOS electrode, (MW), the geometry of which is the same as that of the sense electrodes, and which is also kept at the same potential VSE; Figure 1. The overall transfer characteristic from the voltage applied to the input diode, (and thus the interface potential in the metering well MW) to the amount of image charge produced on the sense electrodes (and hence the output voltage V O ~ T ) can then be expected to be linear. Various possible ways to clamp the sense electrodes to a given potential and to extract the desired output signal have been discussed earlier’’2. A novel approach to extract this difference signal in the presence of the considerably larger common mode signal is shown in Figure 2. One amplifier (AD) performs the differencing operation, while the other amplifier ( Ac) is used to suppress the common mode signal on the two sense busses. AC operates by comparing the arithmetic mean of the sense electrode potentials to the sense voltage reference VSE and feeds back the same error signal to both sense busses through capacitors CCt and Cc. The feedback signal around AD through CDwll maintain the balance between the two sense busses, and the combined","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128684829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}