1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献_第8页

Semiconductor RAMs: Limits to growth 半导体ram:增长的限制

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155729

L. Terman, W. Kosonocky

引用次数: 0

A monolithic IC for decibel-linear noise reduction 一种用于线性降噪的单片集成电路

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155647

H. Yamada, M. Katakura

引用次数: 1

A monolithic companding D/A converter 单片压缩D/A转换器

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155668

J. Schoeff

{"title":"A monolithic companding D/A converter","authors":"J. Schoeff","doi":"10.1109/ISSCC.1977.1155668","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155668","url":null,"abstract":"COMPANDED PULSE CODE MODULATED (PCM) transmission of voice signals has become standardized through widespread use of the Bell system p-law and the CCITT** A-law transfer characteristics. Until now, all codecs (eoder/decoders) for these communication systems have been fabricated in either discrete or hybrid form and have been relatively expensive. This paper will present a newly developed monolithic digital-to-analog converter specifically designed for compression and expansion of signals according to the existing PCM standard. This converter, however, is not limited to PCM communication, but may be used in other areas such as data acquisition, servo controls, data recording, telemetry, voice synthesis, log attenuation, secure communications, sonar, and many other applications which require a 12-bit plus sign dynamic range and the convenience of an 8-bit digital code. When used in a telecommunications application, the companding DAC is a complete PCM decoder, with metal options for p-law and A-law. A one-half step decision level for encoding is provided within the circuit and controlled with the encode/decode logic input. This current offsets the entire transfer characteristic one half step, regardless of the value of the output current. The outputs are multiplexed for time sharing of one DAC for both encode and decode operation. The DAC settling time is 500 ns, and i t will decode more than 32 PCM channels in 125 ps, which is the sampling period at 8 kHz. In a shared encoder it will convert eight channels, assuming a 1 0 ps sample and hold acquisition time. The outputs are high impedance, high compliance current sources and will interface with most balanced loads. The reference inputs will accept a fixed reference or a positive or negative multiplying input. The transfer characteristic of the companding DAC is shown in Figure 1. The output consists of eight positive chords and eight negative chords, each containing sixteen steps. The slopes of these chords are binarily related with the chord at the origin having steps equivalent in size to those in a 12-bit converter. The step size is a nearly constant 3.2% of reading throughout most of the dynamic range, which corresponds to approximately 0.3 dB per step. Each successive chord endpoint is 6 dB below the next higher endpoint for every chord in the A-law specification, and follows this for most chords in the p-law. The dynamic range, or ratio, of the full scale to the smallest step size is 72 dB for the p-law version and 66 dB for the A-law unit. The electrical specifications for the circuit are summarized in Table I.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121733980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

LSI in consumer electronics 消费类电子产品中的大规模集成电路

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155703

S. Mito

引用次数: 0

A 4-GHz 12-W transistor amplifier utilizing a self-aligned bipolar structure 采用自对准双极结构的4 ghz 12 w晶体管放大器

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155715

N. Tsuzuki, Y. Saito, T. Sakai

引用次数: 1

A dual processor serial data controller chip 一种双处理器串行数据控制器芯片

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155634

G. Louie, J. Wipfli, A. Ebright

引用次数: 0

Electrically alterable 8192 bit N-channel MOS PROM 电可变8192位n通道MOS PROM

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155651

R. Muller, H. Nietsch, B. Rossler, E. Wolter

引用次数: 1

Fully ion implanted 4096-bit high speed DSA MOS RAM 全离子注入4096位高速DSA MOS RAM

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155678

K. Shimotori, K. Anami, Y. Nagayama, I. Okhura, M. Ohmori, T. Nakano, Y. Hayashi, Y. Tarui

{"title":"Fully ion implanted 4096-bit high speed DSA MOS RAM","authors":"K. Shimotori, K. Anami, Y. Nagayama, I. Okhura, M. Ohmori, T. Nakano, Y. Hayashi, Y. Tarui","doi":"10.1109/ISSCC.1977.1155678","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155678","url":null,"abstract":"DIFFUSION-SELF-ALIGNED (DM) M O S I C ~ ' , or D M O S ~ have received attention as subnanosecond and high density devices. In this paper, the experimental results of a DSA MOS memory fabricated by full ion implantation techniques to achieve better threshold voltage controllability will be dcscribed. Access time is 60 ns; power consumed is 950mW. Figure 1 shows cross section of the DSA E-D inverter. It is apparent from the figure, that the effective channel region of the DSA transistor is determined by the diffusion length difference between boron and arsenic layer. All dopants were deposited by ion implantatio-n method on P(71) Si substrate; resistivity was 100 \"200 Q-cm, crystal orientation (loo), respectively. The threshold voltage of the device was controlled within 1.20 ? 0.15V and the effective channel length was 0.4 pm. The gain factor was 5 times larger than that of the conventional NMOS3. Features of the DSA MOS process are: 1 ) E-D gate achieved by N-channel 71 planar technique; 2 ) selective oxidation process (SOP) adapted to obtain high packing density and to reduce surface steps; 3) Si gate also used for a smaller feedback capacitance and higher packing density; and 4) all dopants deposited by ion implantation method to improve control of threshold voltage. To evaluate the basic electrical characteristics of these devices, 1 9 stag: ring oscillators have been fabricated by varing process parameters. Figure 2 shows the propagation delay time versus power dissipation, where the parameters were varied for the amount of channel dope to the depletion FET and power supply voltages. In the unhatched region, the driving capability of the DSA MOS FET is smaller than that of the load FET, thus the inverter does not operate. The minimum power delay product (0.05 pJ) and the minimum propagation delay time (0.32 ns) are shown in the ploy. Using this process, a 4096-bit fully decoded dynamic R/W random access memory was developed (Figure 3) using a 5 p m minimum as a base. The memory cell uses a 1 Tr/cell structure to avoid Vth to minimize inverse connection effects due to high __","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120992882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Microprocessors - High end 微处理器——高端

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155743

B. Murphy

引用次数: 0

4-GHz frequency division with GaAs MESFET ICs 采用GaAs MESFET集成电路的4ghz分频

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155641

R. Van Tuyl, C. Liechti, Robert Lee, E. Gowen

引用次数: 15