A 16K × 1 bit dynamic RAM

.4 16K x 1. BIT dynamic RAM capable o f 130-ns access time has bcen developed using a two-level N-channel polysilicon gate process and a single transistor cell. Utilizing the standard 16-pin package configuration, seven address bits are multiplexed. All clocks and othcr inputs are TTI. compatible. Maximum user flexibility has hecn provided by incorporating ___ 2 10% supplies, a nonlatched tri-state data output controlled by CAS, a+ multiplex timing window, page mode capability, and RAS-only refresh. A block diagram o f thc circuit is shown in Figure 1 and a photograph o f a fabricated device appears in Figure 2. The chip is organixcd internallyas a single 128 x 128 balanced array with both column dwodcrs and sense amplifiws located in a row through the center of the array. To maintain a balanced confiqration, each column decode circuit is divided into two parts with one hall on either side of the sense amplifiers. These column dccoders provide 1 of 64 selection. The final 1 of 128 column decoding -is accomplished by selection of one of two ' pairs o f data. data buses which also run through the center, and which are used for IjO coupling to the selected digit circuits. Since acccss is providcd to both the true and complement sense lines associated with each amplifier, no digit pullup transistors are requircd. This permits completely dynamic flipflop type detectors to be uscd, resulting in very low power consumption.