2015 16th International Conference on Electronic Packaging Technology (ICEPT)最新文献

{"title":"A failure analysis on leakage of ceramic capacitor","authors":"J. Cui, Junming Wu","doi":"10.1109/ICEPT.2015.7236671","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236671","url":null,"abstract":"Failure analysis is a comprehensive process which needs to apply kinds of physical and chemistry methods to find out the mechanism. You must learn as more background information as you can, only then could you choose the applicable methods to study the failure sample avoiding disturbance aroused by analysis methods. In this paper, a print circuit board assembly of TV sets which were exported to South America will be analyzed.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125034264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of AgNPs/reduced graphene oxide nanocomposites on the electrical performance of electrically conductive adhesives","authors":"Jinfeng Zeng, Xiaopeng Chen, Xin Ren, Yanqing Ma","doi":"10.1109/ICEPT.2015.7236540","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236540","url":null,"abstract":"Rapid development in electronic products in recent years leads to an increasing demand for electrical conductive adhesives (ECAs) with large electrical conductivity and environmentally friendly. Therefore, how to increase its electrical property meanwhile its other properties can not be affected and even can be enhanced has become the focus of attention. In this study, we chose a green and mild reducing agent glucose, which was synthesised AgNPs/reduced graphene oxide (rGO) nanocomposites based on one-pot method in aqueous solution. The ECAs were prepared by mixing AgNPs/rGO, silver flakes and epoxy. Then we measured the bulk resistivity of ECAs after curing it at 150 °C for two hours. The results showed that when the total amount of the conductive filler maintained at 70 wt%, the mass fraction of AgNPs/rGO reached 0.2 wt%, and the bulk resistivity (8.76×10-5 Ω·cm) was lower than that of filled pure silver flake (1.11×10-4 Ω·cm).","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of the design parameters uncertainty on the PC-white LED color constancy based on the theory of the uncertainty","authors":"Yu-bing Gong, Xianling Zheng, Chao Jin, Defeng Zhang","doi":"10.1109/ICEPT.2015.7236759","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236759","url":null,"abstract":"The white LED color constancy is a challenge for the LED design and packaging. The color binning process is used to deal with this challenge by many manufacturers. The new ideas of “Freedom From Binning” and “Hot testing” were brought out by Philips recently. The Philips approach mainly depended on the Lumiramic phosphor technologies, which improved the uniformity of phosphors coating layer thickness. In this paper, according to the theory of the mix-color, the simulation model was built in MATLAB and the performance of the white LED was analysized based on the model. According to the theory of uncertainty, one uncertainty model of the two primary colors LED's color deviation, correlated color temperature and luminous flux was built which takes the uncertainty of the design parameters, such as the monochromatic spectral wave length, half wave width, into accounting in MATLAB. The probability distribution of the LED color deviation was obtained under the normal probability distribution of the design parameters. The impact of the uncertainty of the design parameters on white LED performance was firstly quantified. The new approach design with improved the LED color constancy was brought out. The paper will give a theoretical and technical foundation of LED color constancy and offer an effective approach for improving the LED color performance.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129988340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electroless plating alloy thin-film embedded resistor materials","authors":"Xingsong Su, Lifei Lai, Chang Li, Wenjun Liu, Xianzhu Fu, R. Sun, C. Wong","doi":"10.1109/ICEPT.2015.7236584","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236584","url":null,"abstract":"Ni-P alloy thin films are prepared by electroless plating as embedded thin-film resistor (ETFR) materials. The micro-structure, electrical, thermal, mechanical, and corrosion-resistant properties of Ni-P alloy thin films are investigated to optimize the electroless plating conditions. When the phosphorus content was greater than 9 %, Ni-P alloy thin films are amorphous. Ni-P alloy thin films' sheet resistance, corrosion resistance and hardness increase with the increase of P content.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129729192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure and viscoelastic behaviors of graphene/PMMA nanocomposites","authors":"Lan-Ying Zhang, Yangwei Zhang","doi":"10.1109/ICEPT.2015.7236533","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236533","url":null,"abstract":"The microstructure and viscoelastic behaviors of graphene filled poly(methyl methacrylate) nanocomposites (graphene/PMMA) have been investigated. The composites were prepared by in situ polymerization method with graphene weight fraction from 0.1 to 1 wt.%. The microstructures were observed by transmitted polarization microscope (TPM) and scanning electron microscope (SEM). The viscoelastic behaviors characterized by storage modulus and loss tangent were measured by dynamic nanoindentation method. The effects of graphene content and force frequency on the viscoelastic behaviors were studied and discussed according to the features of microstructures and mobility of molecular chains. The graphene nanosheets with an average diameter of about 8.6 micrometers are found to disperse homogeneously in the PMMA matrix. The interface between graphene and PMMA is strong and few defects are observed in the impact fracture surfaces of the composites. The results indicate that the microstructure and viscoelastic properties of PMMA polymer are significantly improved by adding a low content of graphene.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116000226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal placement optimization for embedded resistances based on orthogonal design and fuzzy genetic algorithm","authors":"Li Tianming, Zhang Ruibin, Huang Chunyue","doi":"10.1109/ICEPT.2015.7236656","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236656","url":null,"abstract":"Sheet resistance, resistor surface area, distance between the stack embedded resistor layers, distances between the surface of PCB and first layer of embedded resistor layers, distance between the stack embedded resistors in the same layer and current magnitude are selected as six key factors, which affect the temperature distribution. By using orthogonal array, the embedded resistor finite element analysis models which have different configuration parameters' levels combinations are designed. Simulation analysis of temperature field are carried out by using these models. The data of temperatures of stacked embedded resistors are analyzed variance analysis. With 90% of confidence, sheet resistance has the most significant effect on the temperature. Therefore, the research object is sheet resistance layout of resistance element in embedded substrate, which is optimizated by Fuzzy Genetic Algorithm The optimization result has more equal distribution of temperature, both of the highest temperature and the maximum temperature difference have a significant decrease. The effectiveness of the algorithm is verified by testing the temperature distribution of experimental samples through the infrared thermometer.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122925405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Classification and 3D stack of Embedded Components technology in Substrate","authors":"Zhicheng Yang, Ferlee Gunawan, X. Gu, Kunpeng Ding, Hao He","doi":"10.1109/ICEPT.2015.7236674","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236674","url":null,"abstract":"Recently, Embedded Components in Substrates (ECiS) technology has been developed with many technologies. Some of these technologies are very mature and compatible for any conventional processes of PCB/Substrate manufacturing which need to be supported by SMT processes. Nowadays, some of electronic products with ECiS technologies already got high volume production scale. As frontline, this paper will describe about the classification of these ECiS technologies. As the development of ECiS technologies into the 3D stacking generation, there are 3 major options had been researched and developed by the industry. One of the options uses a combined process of two different ECiS technologies (via technique and vialess technique) as a new solution which will provide more possibility to decrease the size of the Integrated Circuit Products with more complexly system integration, much higher reliability and more simply interconnection, all these will dramatically improve the electrical performance. By combining the advantages of via technique and via-less technique, an optimized technique has been developed for the ECiS technology. We designed test boards with daisy chain die and the manufacturing process is demonstrated as follow. A specific requirement for Pad metallization of dies was prepared with RDL technique firstly, after that one of the dies was embedded with blind via technique and then followed solder joint technique for the other die to accomplish the stacking process completely. This thin test board structure with embedded 2 stacking dies and very short path for interconnection between the stack dies would be discussed with more details in last section of this paper. At last, some key reliability test items (such as Moisture Sensitivity Test in Level 3 with 5 times Assembly Rework and Thermal Cycling Test) were applied to analyze the reliability of these test boards in details. Also the electrical test and Scanning Acoustic Microscope (SAM) for both before and after the reliability test showed very good results.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124080494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leadframes' AuAg plating thickness influences to stitch bonding of palladium coated copper wires","authors":"Sock Chien Tey, K. Lau, Mohd Edderozey Abd Manaf","doi":"10.1109/ICEPT.2015.7236555","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236555","url":null,"abstract":"Palladium coated copper (PCC) wire bonding on roughen preplated leadframe is a preferred electrical interconnect in the semiconductor package due to its robustness package performances. PCC wire is replacing bare copper wires to eliminate the copper oxidation problem. Whereas, roughen treated preplated leadframe is used to eliminate post-plating of leadframe as well as to enhance the adhesion of leadframe to the epoxy mold compounds. However, role of the plating thickness of roughen preplated leadframe on the PCC wire has not yet been fully understood. Thus, this paper investigates stitch bonding strength of PCC wire on the AuAg/Pd/Ni/Cu preplated leadframe with different AuAg plating thickness. Stitch pull test results on PCC wire bonding on different preplated leadframe showed higher stitch bonding strength for samples with higher AuAg plating thickness. Optical micrographs showed mechanical failure at bond heel of test sample, due to higher tensile stress during the pull test. Thicker AuAg layers may provide greater cushioning effect against wire deformation at bond heel during stitch bonding process. This in turns increased the stitch bonding strength of the PCC wire bond. STEM micrograph and EDX line-scan profile in all samples showed formation of interdiffusion zone at the PCC wire/ leadframe bonding interface. At the distinct bonding interface, interdiffusion zone extended from Pd layer of PCC wire to Pd layer of leadframe, where Pd species from both sides were intermixed. Whereas at blurred bonding interface, interdiffusion zone was extended further to Pd/Ni interface region. Formation of interdiffusion zone may strengthened wire bond between the PCC wire and the leadframe, thus prevented bond delamination during the stitch pull strength test.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121491962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Au-Ag bonding for 3D stacked package","authors":"Long Zhang, Jian Cai, Lin Tan, Qian Wang, Songliang Jia","doi":"10.1109/ICEPT.2015.7236707","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236707","url":null,"abstract":"Bipolar transistor is widely applied in the field of power electronics. However, there still exist many difficulties to manufacture high voltage Bipolar transistor nowadays. One of the approaches that can improve the withstand voltage of the Bipolar transistor is to stack multiple low-withstand voltage bipolar chips. SiC Schottky diode is bipolar transistor with aluminum electrode as anode and silver electrode as cathode. The purpose of this work was to realize the 3D die stacking by Au-Ag thermocompression bonding of two chips with the same electrode structure as SiC Schottky Diode. Gold stud bumps were made on the aluminum electrode by thermosonic bonding. Two chips were stacked together by Au-Ag thermocompression bonding. Different bonding parameters and annealing conditions were evaluated. Experiment results showed that increasing bonding temperature or annealing duration could improve the bonding quality. The Au-Ag bonding with 15N bond load at 250°C for 20 minutes followed by nitrogen annealing at 160°C for 30 minutes exhibited a successful bonding performance. The Au-Ag bonding interface was analyzed by SEM (scanning electron microscope) and EDX (energy dispersive x-ray spectroscope). Continuous alloy compositions were observed by atomic diffusion between gold and silver.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132221782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon carbide power electronic module packaging","authors":"He Shaowei, Longcheng Que, L. Jian, S. Ang","doi":"10.1109/ICEPT.2015.7236632","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236632","url":null,"abstract":"Wide bandgap semiconductors such as gallium nitride (GaN) and silicon carbide (SiC) offer exciting opportunities in enhancing the performance of power electronic systems in term of improved efficiency as well as higher temperature operation. Both silicon carbide and gallium nitride power semiconductor devices offer a higher voltage handling capability over their silicon power semiconductor counterparts. In this paper, the design and packaging issues for SiC power electronic modules are discussed. Several SiC devices are usually connected in parallel to increase its current handling capability in power electronic module packaging. The paralleling of these SiC devices creates unbalanced parasitic inductances which affect the dynamic switching performance for these paralleled devices. Each of the paralleled SiC devices could have different initial peak currents due to their different parasitic inductances within the module. Moreover, their fast dv/dt of the drain voltages as well as the high di/dt of the drain currents can cause spurious switching behaviors in some of the paralleled SiC devices in the power module. Layout techniques can be used to mitigate these spurious switching behaviors. However, module construction architectures and as well as module package construction are required to further mitigate these parasitic inductances. One of the many advantages of the SiC power devices is high voltage handling capability. High voltage operation of the power electronic module requires careful reduction of electric field intensification within the device as well as the module. Encapsulations with the desired dielectric breakdown strength as well as temperature performance must be applied on top of these devices to prevent premature voltage breakdown. One of the salient features of the SiC power electronic modules is high temperature operation of greater than 175°C. For high temperature operations, proper die attach must be utilized. Nano silver sintering and transient liquid phase bonding are two high temperature die attachment techniques. For high temperature operation, reliability testing for these SiC power electronic modules must be carefully considered since there is no existing international standard for reliability testing for these high-temperature power electronic modules.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134312031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}