Zhicheng Yang, Ferlee Gunawan, X. Gu, Kunpeng Ding, Hao He
{"title":"Classification and 3D stack of Embedded Components technology in Substrate","authors":"Zhicheng Yang, Ferlee Gunawan, X. Gu, Kunpeng Ding, Hao He","doi":"10.1109/ICEPT.2015.7236674","DOIUrl":null,"url":null,"abstract":"Recently, Embedded Components in Substrates (ECiS) technology has been developed with many technologies. Some of these technologies are very mature and compatible for any conventional processes of PCB/Substrate manufacturing which need to be supported by SMT processes. Nowadays, some of electronic products with ECiS technologies already got high volume production scale. As frontline, this paper will describe about the classification of these ECiS technologies. As the development of ECiS technologies into the 3D stacking generation, there are 3 major options had been researched and developed by the industry. One of the options uses a combined process of two different ECiS technologies (via technique and vialess technique) as a new solution which will provide more possibility to decrease the size of the Integrated Circuit Products with more complexly system integration, much higher reliability and more simply interconnection, all these will dramatically improve the electrical performance. By combining the advantages of via technique and via-less technique, an optimized technique has been developed for the ECiS technology. We designed test boards with daisy chain die and the manufacturing process is demonstrated as follow. A specific requirement for Pad metallization of dies was prepared with RDL technique firstly, after that one of the dies was embedded with blind via technique and then followed solder joint technique for the other die to accomplish the stacking process completely. This thin test board structure with embedded 2 stacking dies and very short path for interconnection between the stack dies would be discussed with more details in last section of this paper. At last, some key reliability test items (such as Moisture Sensitivity Test in Level 3 with 5 times Assembly Rework and Thermal Cycling Test) were applied to analyze the reliability of these test boards in details. Also the electrical test and Scanning Acoustic Microscope (SAM) for both before and after the reliability test showed very good results.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEPT.2015.7236674","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Recently, Embedded Components in Substrates (ECiS) technology has been developed with many technologies. Some of these technologies are very mature and compatible for any conventional processes of PCB/Substrate manufacturing which need to be supported by SMT processes. Nowadays, some of electronic products with ECiS technologies already got high volume production scale. As frontline, this paper will describe about the classification of these ECiS technologies. As the development of ECiS technologies into the 3D stacking generation, there are 3 major options had been researched and developed by the industry. One of the options uses a combined process of two different ECiS technologies (via technique and vialess technique) as a new solution which will provide more possibility to decrease the size of the Integrated Circuit Products with more complexly system integration, much higher reliability and more simply interconnection, all these will dramatically improve the electrical performance. By combining the advantages of via technique and via-less technique, an optimized technique has been developed for the ECiS technology. We designed test boards with daisy chain die and the manufacturing process is demonstrated as follow. A specific requirement for Pad metallization of dies was prepared with RDL technique firstly, after that one of the dies was embedded with blind via technique and then followed solder joint technique for the other die to accomplish the stacking process completely. This thin test board structure with embedded 2 stacking dies and very short path for interconnection between the stack dies would be discussed with more details in last section of this paper. At last, some key reliability test items (such as Moisture Sensitivity Test in Level 3 with 5 times Assembly Rework and Thermal Cycling Test) were applied to analyze the reliability of these test boards in details. Also the electrical test and Scanning Acoustic Microscope (SAM) for both before and after the reliability test showed very good results.