2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第2页

Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level 实时操作系统级并发内存bist执行的在线调度

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962338

F. Angione, P. Bernardi, Gabriele Filipponi, Claudia Tempesta, M. Reorda, D. Appello, V. Tancorre, R. Ugioli

{"title":"Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level","authors":"F. Angione, P. Bernardi, Gabriele Filipponi, Claudia Tempesta, M. Reorda, D. Appello, V. Tancorre, R. Ugioli","doi":"10.1109/DFT56152.2022.9962338","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962338","url":null,"abstract":"Automotive System-on-Chip (SoC) performances have enormously increased in the last decade. Therefore, bare-metal safety-critical applications have shifted to the new application paradigm written at the Operating System layer, i.e., on top of Real-Time Operating Systems (RTOS). The RTOS stores needed data and instructions in the embedded memories. Therefore, potential corruption in these memories could generate non-deterministic, wrong behaviors. Online software or hardware testing mechanisms detect and sometimes correct such dangerous situations. In either case, the application programmer has to devise special tasks devoted to testing and must ensure fully working synchronization mechanisms without impacting the feasibility of the RTOS scheduler. This paper investigates the impact on the scheduling and reliability of an RTOS when hardware and software memory BIST periodically test embedded RAMs in the field. The results are obtained on a real automotive SoC belonging to the SPC58 family from ST Microelectronics.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131773445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening RADPlace-MS:用于asic辐射硬化的定时驱动砂矿机和优化器

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962347

C. Georgakidis, S. Simoglou, C. Sotiriou

{"title":"RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening","authors":"C. Georgakidis, S. Simoglou, C. Sotiriou","doi":"10.1109/DFT56152.2022.9962347","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962347","url":null,"abstract":"The manufacturing of modern Integrated Circuits (ICs), resistant against faults caused by ionising radiation, has become quite challenging due to the rapid advancement of VLSI technology. Additionally, the Radiation Hardening process, which involves making electronic cells and circuits resistant to damage or faults induced by ionising radiation, deviates from the conventional design flow. Thus, it generally suffers from insufficient support from industrial EDA tools. RADPlace is an academic timing-driven detailed placement algorithm that ensures spacing constraints among TMR triplet members. However, RADPlace, considering only the top critical paths of the circuit, limits the improvement in circuit timing, especially Total Negative Slack (TNS). In this work, we propose an improved RADPlace version (RADPlace-I) and a Multi-Step RADPlace version (RADPlace-MS), separating timing-driven optimisations from the placement step. Experimental results indicate that RADPlace-I achieves an average 21% improvement in Worst Negative Slack (WNS), while it achieves TNS improvement in most cases. On the other hand, RADPlace-MS achieves an average 54% and 45% improvement in WNS and TNS, respectively, compared to the original RADPlace version, with negligible impact on circuit total area and power.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130539673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE) 基于超奇异同源密钥交换(SIKE)的高效环中断故障攻击

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962359

Piyush Beegala, Debapriya Basu Roy, P. Ravi, S. Bhasin, A. Chattopadhyay, Debdeep Mukhopadhyay

{"title":"Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE)","authors":"Piyush Beegala, Debapriya Basu Roy, P. Ravi, S. Bhasin, A. Chattopadhyay, Debdeep Mukhopadhyay","doi":"10.1109/DFT56152.2022.9962359","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962359","url":null,"abstract":"Post-quantum secure public key algorithm Super-singular Isogeny based Key Exchange (SIKE) has emerged as a viable candidate for post-quantum secure key encapsulation mechanism. SIKE is based on isogeny property of elliptic curves and its security depends upon the intractability of computing the isogenous path from the source and image curve. In this paper, we focus on the vulnerability of SIKE against fault attacks, specifically against loop abort fault attacks. The fault attacks proposed in this paper can be applied to both naive and optimized implementations of large degree isogeny computation. The attack on naive implementation is based on creating loop abort faults during scalar multiplication and isogeny computation. The effectiveness of such loop abort faults is twofold: it can transform the post-quantum hardness of SIKE to a post-quantum vulnerable ECDLP (Elliptic Curve Discrete Log), while in the other case the adversary can retrieve the secret key of SIKE protocol with little computational effort. The attack on optimized implementation of SIKE takes advantage of the publicly available computation strategy of isogeny computation. Therefore, it can recover the private key of SIKE with only a few fault injections.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128061341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU HPMA-NTRU:高性能多项式乘法加速器NTRU

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962336

Pengzhou He, Yazheng Tu, A. Khalid, Máire O’Neill, Jiafeng Xie

{"title":"HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU","authors":"Pengzhou He, Yazheng Tu, A. Khalid, Máire O’Neill, Jiafeng Xie","doi":"10.1109/DFT56152.2022.9962336","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962336","url":null,"abstract":"Along the rapid development of large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from research community recently as it is proven that the existing public-key cryptosystems are vulnerable to the quantum attacks. Meanwhile, the recent trend in the PQC field has gradually switched to the hardware acceleration aspect. Following this trend, this work presents a novel implementation of a High-performance Polynomial Multiplication hardware Accelerator for NTRU (HPMA-NTRU) under different parameter settings, one of the lattice-based PQC algorithm that is currently under the consideration by the National Institute of Standards and Technology (NIST) PQC standardization process. In total, we have carried out three layers of efforts to obtain the proposed work. First of all, we have proposed a new schoolbook algorithm based strategy to derive the desired polynomial multiplication algorithm for NTRU. Then, we have mapped the algorithm to build a high-performance polynomial multiplication hardware accelerator and have extended this hardware accelerator to different parameter settings with proper adjustment. Finally, through a series of complexity analysis and implementation based comparison, we have shown that the proposed hardware accelerator obtains better area-time complexities than the state-of-the-art one. The outcome of this work is important and will impact the ongoing NIST PQC standardization process and can be deployed further to construct efficient NTRU cryptoprocessors.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124001265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SET Hardened Derivatives of QDI Buffer Template 设置QDI缓冲模板的硬化衍生物

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962344

Zaheer Tabassam, A. Steininger

{"title":"SET Hardened Derivatives of QDI Buffer Template","authors":"Zaheer Tabassam, A. Steininger","doi":"10.1109/DFT56152.2022.9962344","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962344","url":null,"abstract":"As critical charges become smaller due to technology advancement, Single Event Transients (SET’s) become more threatening to circuits. Quasi Delay-Insensitive (QDI) circuits are tolerant against timing issues, but they tend to be more sensitive towards transients – and hence SET’s – in the value domain. This can be somewhat mitigated, without sacrificing their delay insensitivity, by shortening their sensitive data acceptance windows. In this paper we investigate these sensitive areas in search of possible ways to specifically harden buffer stages, as these are elementary for building asynchronous pipelines and play a major role in the manifestation of an SET as a Single Event Upset (SEU). Inspired from existing work in the literature, we propose a buffer template called “Dual CD IN/OUT Interlock WCHB” that is basically a hybrid approach to smartly shorten the sensitive window. It reduces the cases where existing approaches fail by up to 5% magnitude. Further investigation suggests some improvement in the design, namely the “Dual CD IN/OUT Interlock WCHB Simplified” which leads to up to 44% area savings without effecting the core resilience. The enhancements are verified in simulation with realistic circuits like Multiplier, ALU, and FIFO under a timing model from the NanGate 15nm library.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127241939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies 基于模型的基于FinFET技术的6T SRAM单事件干扰(SEU)漏洞分析

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962348

Semiu A. Olowogemo, Hao Qiu, B. Lin, W. H. Robinson, D. Limbrick

引用次数: 0

Selective Hardening of CNNs based on Layer Vulnerability Estimation 基于层脆弱性估计的cnn选择性加固

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962339

C. Bolchini, Luca Cassano, A. Miele, Alessandro Nazzari

引用次数: 3

Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems 多处理器系统下深度神经网络故障仿真中的线程级并行性

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962358

Masoomeh Karami, M. Haghbayan, M. Ebrahimi, A. Miele, J. Plosila

{"title":"Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems","authors":"Masoomeh Karami, M. Haghbayan, M. Ebrahimi, A. Miele, J. Plosila","doi":"10.1109/DFT56152.2022.9962358","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962358","url":null,"abstract":"High-performance fault simulation is one of the essential and preliminary tasks in the process of online and offline testing of machine learning (ML) hardware. Deep neural networks (DNN), as one of the essential parts of ML programs, are widely used in many critical and non-critical applications in Systems-on-Chip and ASIC designs. Through fault simulation for DNNs, by increasing the number of neurons, the fault simulation time increases exponentially. However, the software architecture of neural networks and the lack of dependency between neurons in each inference layer provide significant opportunity for parallelism of the fault simulation time in a multi-processor platform. In this paper, a multi-thread technique for hierarchical fault simulation of neural network is proposed, targeting both permanent and transient faults. During the process of fault simulation the neurons for each inference layer will be distributed among the executing threads. Since in the process of hierarchical fault simulation, the faulty neuron demands proportionally enormous computation comparing to behavioural model of non-faulty neurons, the faulty neuron will be assigned to one thread while the rest of the neurons will be divided among the remaining threads. Experimental results confirm the time efficiency of the proposed fault simulation technique on multi-processor architectures.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Storage-Based Logic Built-In Self-Test with Variable-Length Test Data 基于存储的逻辑内置自检与变长测试数据

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962357

I. Pomeranz

引用次数: 0

Understanding time-varying vulnerability accross GPU Program Lifetime 理解跨GPU程序生命周期的时变漏洞

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962365

Hao Qiu, Semiu A. Olowogemo, B. Lin, W. H. Robinson, D. Limbrick

引用次数: 0