2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第3页

X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective x射线故障注入:从安全角度回顾防御方法

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962362

Nasr-Eddine Ouldei Tebina, N. Zergainoh, P. Maistri

引用次数: 2

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip 一种容错RISC-V片上系统的中子辐照测试与分析

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962335

D. Santos, André M. P. Mattos, Lucas Matana Luza, C. Cazzaniga, M. Kastriotou, D. Melo, L. Dilillo

{"title":"Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip","authors":"D. Santos, André M. P. Mattos, Lucas Matana Luza, C. Cazzaniga, M. Kastriotou, D. Melo, L. Dilillo","doi":"10.1109/DFT56152.2022.9962335","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962335","url":null,"abstract":"The radiation in harsh environments affects electronic systems, inducing permanent and temporary errors. These effects lead to unpredictable behaviors detrimental to critical applications and fail-safe systems. This work evaluates the reliability of a fault-tolerant RISC-V System-on-Chip (SoC) under atmospheric neutron irradiation in a particle accelerator. Prior work has analyzed the effectiveness of the hardening techniques of this SoC in simulation and provided a preliminary characterization in an irradiation facility. The applied hardening techniques showed a significant reliability improvement compared to the unhardened implementation of the SoC. The system executed a performance benchmark as workload, which finished correctly in most runs despite suffering from Single Event Effects (SEEs). This work presents a detailed analysis of the experimental results, reporting error rates and classification, extending the analysis given in previous works. Finally, a comprehensive discussion of implementation limitations and the proposition of further improvements are provided.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132136146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Is RISC-V ready for Space? A Security Perspective RISC-V为太空做好准备了吗?安全视角

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962352

Luca Cassano, Stefano Di Mascio, A. Palumbo, A. Menicucci, G. Furano, Giuseppe Bianchi, M. Ottavi

{"title":"Is RISC-V ready for Space? A Security Perspective","authors":"Luca Cassano, Stefano Di Mascio, A. Palumbo, A. Menicucci, G. Furano, Giuseppe Bianchi, M. Ottavi","doi":"10.1109/DFT56152.2022.9962352","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962352","url":null,"abstract":"Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130817769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Aging Effects On Clock Gated Memory Phase Paths 时钟门控记忆相位路径的老化效应

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962342

Amlan Ghosh, Saroj Satapathy, J. Kulkarni, Prashant D. Joshi

{"title":"Aging Effects On Clock Gated Memory Phase Paths","authors":"Amlan Ghosh, Saroj Satapathy, J. Kulkarni, Prashant D. Joshi","doi":"10.1109/DFT56152.2022.9962342","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962342","url":null,"abstract":"Transistor aging is a critical reliability issue affecting all nanoscale designs in advanced CMOS technologies. The aging affects the electrical properties of the transistors over time, degrading its performance depending on the amount of aging stress. In this work, we have specifically addressed the issue of clock duty cycle modulation in gated clock decoding paths due to asymmetric aging effects. If this degradation occurs in the duty cycle of the clock, the effects will be more pronounced in phase-based paths, rather than cycle time-based paths. Register File designs often have many phase-based paths which may experience performance degradation. This work describes the clock duty cycle aging issue in phase-based memory designs and proposes a low-cost solution that can be added to all the memory array instances, depending on the size of the individual instance. The proposed clock duty cycle adjustment can be based on the aging stress (clock gating) experienced by the individual array. It will enable the low-phase operations such as precharge and wakeup from becoming timing critical with the transistor aging. This mitigates the problem of running at a lower frequency considering the cumulative aging effects during the operational lifetime, or alternately designing to more stringent delay constraints which increase power overheads. Simulation results with advanced sub10nm FinFET CMOS, shows 5% frequency improvement while operating at standard Vcc over five years of aging stress with 10% activity in an 8-stage clock gated Register File memory decoding path.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"306 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124283742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Toward the hardening of real-time operating systems 朝着强化实时操作系统的方向发展

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962356

A. Bosio, S. Carlo, Maurizio Rebaudengo, A. Savino

引用次数: 1

Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained Networks 基于预训练网络的深度学习侧信道攻击隐藏对策评估

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962360

Konstantinos Nomikos, Athanasios Papadimitriou, M. Psarakis, A. Pikrakis, V. Beroulle

{"title":"Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained Networks","authors":"Konstantinos Nomikos, Athanasios Papadimitriou, M. Psarakis, A. Pikrakis, V. Beroulle","doi":"10.1109/DFT56152.2022.9962360","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962360","url":null,"abstract":"In recent years, the emerging technology of machine learning has been taken into advantage to implement powerful Side Channel Analysis (SCA) attacks. By means of Deep Learning (DL) SCA attacks, countermeasures previously considered strong, such as masking, have failed to provide adequate security levels. This fact creates the need of taking attacks based on artificial neural networks into account during the design of cryptographic implementations. To make things worse, such neural networks may be pre-trained so as to succeed in attacking multiple implementations of a given cipher which were even not used during the training phase. To this end, this work evaluates two low-overhead SCA countermeasure techniques, which add noise in the calculation of the cryptographic algorithm to protect it against DL-SCA attacks with pre-trained networks. We propose the use of two existing, low-overhead countermeasure techniques and evaluate their resilience against multiple pre-trained DL-based SCA networks published in the literature. We show that the pre-trained networks which have been trained with power traces from an unprotected cipher implementation can be used to compromise the protection of a single hiding countermeasure but not the combination of the two hiding countermeasures. This is also true when the model has been pre-trained using a cipher implementation with a single hiding countermeasure. Thus, the combination of these two offers increased protection against pre-trained networks with low associated overheads","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124972258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process 嵌入式进程片上存储器中质子诱导的单事件效应分析

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-10-19 DOI: 10.1109/DFT56152.2022.9962341

C. D. Sio, S. Azimi, L. Sterpone, D. M. Codinachs

引用次数: 2

Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography 基于格密码的积分采样器和多项式乘法结构

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-08-30 DOI: 10.1109/DFT56152.2022.9962361

Antian Wang, Weihang Tan, K. Parhi, Yingjie Lao

引用次数: 1

INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling INTERPLAY:一个预测由于多缓存方式禁用导致的性能下降的智能模型

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-06-23 DOI: 10.1109/DFT56152.2022.9962363

Panagiota Nikolaou, Yiannakis Sazeides, M. Michael

引用次数: 0

MetaFS: Model-driven Fault Simulation Framework MetaFS:模型驱动故障仿真框架

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2022-04-27 DOI: 10.1109/DFT56152.2022.9962369

Endri Kaja, Nicolas Gerlin, Luis Rivas, M. Bora, Keerthikumara Devarajegowda, W. Ecker

{"title":"MetaFS: Model-driven Fault Simulation Framework","authors":"Endri Kaja, Nicolas Gerlin, Luis Rivas, M. Bora, Keerthikumara Devarajegowda, W. Ecker","doi":"10.1109/DFT56152.2022.9962369","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962369","url":null,"abstract":"The adoption of new technologies by the automotive industry drives the need for electronic component suppliers to assess and scrutinize the risk of technologies that are being integrated into the safety-critical systems. To cope with these challenges, engineers are constantly looking for highly automated and efficient functional safety approaches to achieve the required certifications for their designs. In this paper, we propose MetaFS, a metamodel-based simulator-independent fault simulation framework that provides multi-purpose fault injection strategies such as statistical fault injection, direct fault injection, and exhaustive fault injection. The framework enables the injection of stuck-at faults, single-event transients, single-event upsets as well as timing faults. The proposed approach scales to a wide range of RISC-V based CPU subsystems with support for various RISC-V ISA standard extensions and, additional safety and security related custom instruction extensions. The subsystems were running the Dhrystone application and a specific in-house Fingerprint calculation application respectively. A minimal effort of 1 person-day was required to conduct 22 different fault simulation campaigns, providing significant data regarding subsystem failure rates.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114853292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2