Aging Effects On Clock Gated Memory Phase Paths

Abstract

Transistor aging is a critical reliability issue affecting all nanoscale designs in advanced CMOS technologies. The aging affects the electrical properties of the transistors over time, degrading its performance depending on the amount of aging stress. In this work, we have specifically addressed the issue of clock duty cycle modulation in gated clock decoding paths due to asymmetric aging effects. If this degradation occurs in the duty cycle of the clock, the effects will be more pronounced in phase-based paths, rather than cycle time-based paths. Register File designs often have many phase-based paths which may experience performance degradation. This work describes the clock duty cycle aging issue in phase-based memory designs and proposes a low-cost solution that can be added to all the memory array instances, depending on the size of the individual instance. The proposed clock duty cycle adjustment can be based on the aging stress (clock gating) experienced by the individual array. It will enable the low-phase operations such as precharge and wakeup from becoming timing critical with the transistor aging. This mitigates the problem of running at a lower frequency considering the cumulative aging effects during the operational lifetime, or alternately designing to more stringent delay constraints which increase power overheads. Simulation results with advanced sub10nm FinFET CMOS, shows 5% frequency improvement while operating at standard Vcc over five years of aging stress with 10% activity in an 8-stage clock gated Register File memory decoding path.