2016 International Symposium on Rapid System Prototyping (RSP)最新文献

A HW/SW embedded system for accelerating diagnosis of glaucoma from eye fundus images 基于眼底图像加速青光眼诊断的硬件/软件嵌入式系统

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990303

P. Dantas, Andrea Sarmento, Adriano Sarmento

引用次数: 3

HAMEX: heterogeneous architecture and memory exploration framework HAMEX:异构架构和内存探索框架

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990316

Kasra Moazzemi, Chen-Ying Hsieh, N. Dutt

{"title":"HAMEX: heterogeneous architecture and memory exploration framework","authors":"Kasra Moazzemi, Chen-Ying Hsieh, N. Dutt","doi":"10.1145/2990299.2990316","DOIUrl":"https://doi.org/10.1145/2990299.2990316","url":null,"abstract":"The increasing amount of computation in heterogeneous architectures (including CPU and GPU cores) puts a big burden on memory subsystem. With the gap between compute units and the memory performance getting wider, designing a platform with a responsive memory system becomes more challenging. This issue is exacerbated when memory systems have to satisfy a high volume of traffic generated from heterogeneous compute units. Furthermore, as emerging memory technologies are being introduced to address these issues, a rapid and flexible mechanism is needed to evaluate these technologies in the context of heterogeneous architectures. This paper proposes HAMEX, a framework that enables early design space exploration of heterogeneous systems with a focus on resolving memory access bottlenecks. This framework first allows system designers to easily model heterogeneous architectures that can run both CPU and GPU workloads. Next, given a set of workloads partitioned on various compute units, traffic generated by these units are captured in order to explore different memory systems. We show the feasibility of design space exploration using HAMEX by simulating a contemporary commercial heterogeneous platform and explore the opportunities for power and performance improvements by adopting different memory technologies.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125904562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Automatic detection and elision of reset sub-circuits 自动检测和省略复位子电路

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990305

Panagiotis Patros, K. Kent

{"title":"Automatic detection and elision of reset sub-circuits","authors":"Panagiotis Patros, K. Kent","doi":"10.1145/2990299.2990305","DOIUrl":"https://doi.org/10.1145/2990299.2990305","url":null,"abstract":"Electronic circuits are too complex to be designed by hand so hardware languages, like Verilog, and Computer Aided Design (CAD) tools are used for these purposes. Two main types of circuits are Application-Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). ASICs require a reset sub-circuit to initialize their state; however, such a procedure is not necessary for FPGAs that support power-on reset. We propose and evaluate a tool that automatically detects and elides reset sub-circuits as part of the Verilog-to-Routing (VTR) CAD flow and in particular Odin II. Also, our tool can be used to decide if a reset sub-circuit has been properly implemented and can point towards memory components that have not been initialized. Such a tool is the first to our knowledge. Our tests with the VTR Verilog benchmarks and other Verilog circuits showed significant reductions in resource consumption on the target FPGAs as much as 25.9% shorter critical path, 90.39% shorter maximum net, 62.84% fewer used logic blocks and 30.87% fewer used routing elements. Also, our approach yielded significant reductions in the execution time of the placement-and-routing algorithm for the elided circuits that were as high as 4.5 times faster VPR execution and 3.35 times faster overall VTR flow execution.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126140704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

RapidSoC: short turnaround creation of FPGA based SoCs RapidSoC:基于FPGA的soc的短周期创建

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990314

Jakob Wenzel, C. Hochberger

引用次数: 4

Inter-FPGA routing environment for performance exploration of multi-FPGA systems 用于多fpga系统性能探索的fpga间路由环境

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990317

U. Farooq, R. Chotin-Avot, M. Azeem, Maminionja Ravoson, M. Turki, H. Mehrez

{"title":"Inter-FPGA routing environment for performance exploration of multi-FPGA systems","authors":"U. Farooq, R. Chotin-Avot, M. Azeem, Maminionja Ravoson, M. Turki, H. Mehrez","doi":"10.1145/2990299.2990317","DOIUrl":"https://doi.org/10.1145/2990299.2990317","url":null,"abstract":"Multi-FPGA platforms are a popular choice today for complex system prototyping because they offer high execution speed, low cost, and real world testing experience. However, performance of multi-FPGA based systems is severely affected by widening logic to I/O gap in FPGAs. In order to address the performance issue, in this work, we propose an exploration and optimization flow for multi-FPGA based prototyping that gives an end-to-end experience starting from benchmark generation to optimized inter- FPGA routing. Using generic tools of the flow, ten large benchmarks are generated. Then, through a generic novel inter-FPGA routing environment, effect of variation of number of FPGAs as well as number of inter-FPGA tracks on the performance of a target design is explored. For performance exploration and optimization, five different FPGA boards are utilized where number of FPGAs on board are varied from two to six. Moreover, for each board four different inter-FPGA track combinations are used. Experimental results reveal that multi-FPGA boards with inter-FPGA tracks corresponding optimally to the cut net requirements of benchmarks under consideration give best frequency results. Furthermore, frequency comparison between different boards shows that FPGA board with six FPGAs gives, on average, best frequency results. Finally, we also perform frequency-price analysis which shows that board with four FPGAs gives better frequency-price tradeoff as compared to other FPGA boards under consideration.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121424575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Schedulability-guided exploration of multi-core systems 多核系统的可调度性引导探索

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990319

Rabeh Ayari, Imane Hafnaoui, G. Beltrame, G. Nicolescu

{"title":"Schedulability-guided exploration of multi-core systems","authors":"Rabeh Ayari, Imane Hafnaoui, G. Beltrame, G. Nicolescu","doi":"10.1145/2990299.2990319","DOIUrl":"https://doi.org/10.1145/2990299.2990319","url":null,"abstract":"Efficient mapping of tasks onto heterogeneous multi-core systems is very challenging especially under hard timing constraints. Assigning tasks to processors is an NP-hard problem and solving it requires the use of meta-heuristics. Relevantly, genetic algorithms have already proven to be one of the most powerful and widely used stochastic tools to solve this problem. Conventional genetic algorithms were initially defined as a general evolutionary algorithm based on blind operators. It is commonly admitted that the use of these operators is quite poor for an efficient exploration. Likewise, since exhaustive exploration of the solution space is unrealistic, a potent option is often to guide the exploration process by hints, derived by problem structure. This guided exploration prioritizes fitter solutions to be part of next generations and avoids exploring unpromising configurations by transmitting a set of predefined criteria from parents to children. Consequently, genetic operators, such as crossover, must incorporate specific domain knowledge to intelligently guide the exploration of the solution space. In this paper, we illustrate and evaluate the impact of crossover operators and we propose a hybrid genetic algorithm based on a novel schedulability-guided operator that easily outperforms the classical operators by offering at least 21% improvement in terms of ratio of certainly schedulable tasks.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116609976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Efficient parallel multi-objective optimization for real-time systems software design exploration 面向实时系统软件设计探索的高效并行多目标优化

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990310

Rahma Bouaziz, L. Lemarchand, Frank Singhoff, Bechir Zalila, M. Jmaiel

{"title":"Efficient parallel multi-objective optimization for real-time systems software design exploration","authors":"Rahma Bouaziz, L. Lemarchand, Frank Singhoff, Bechir Zalila, M. Jmaiel","doi":"10.1145/2990299.2990310","DOIUrl":"https://doi.org/10.1145/2990299.2990310","url":null,"abstract":"Real-time embedded systems may be composed of a large number of time constrained functions. During software architecture design, these functions must be assigned to tasks that will run the functions on the top of a real-time operating systems (RTOS). This is a challenging work due to the large number of valid candidate functions to tasks assignment solutions. Moreover, the impact of the assignment on the system performance criteria (often conflicting) should be taken into account in the architecture exploration. The automation of the design exploration by the use of metaheuristics such as multi-objective evolutionary algorithm (MOEA) is a suitable way to help the designers. MOEAs approximate near-optimal alternatives at a reasonable time when compared to an exact search method. However, for large-scale systems even a MOEA method is impractical due to the increased time required to solve a problem instance. To tackle this problem, we present in this article a parallel implementation of the Pareto Archived Evolution Strategy (PAES) algorithm used as a MOEA for the design exploration. The proposed parallelization method is based on the well-known Master-Slave paradigm. Additionally, it involves a new selection scheme in the PAES algorithm. Results of experimentations provide evidence that, on one hand, the parallel approach can considerably speed up the design exploration and the optimization processes. On the other hand, the proposed selection strategy improves the quality of obtained solutions as compared to the original PAES selection schema.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116563663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Rapid SOC prototyping utilizing quilt packaging technology for modular functional IC partitioning 快速SOC原型利用被子封装技术的模块化功能IC划分

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990313

Tian Lu, Carlos Ortega, J. Kulick, G. Bernstein, Scott Ardisson, Rob Engelhardt

引用次数: 2

Architecture exploration of intelligent robot system using ros-compliant FPGA component 基于ros-compliant FPGA组件的智能机器人系统架构探索

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990312

Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, K. Ootsu, T. Yokota

引用次数: 13

Transforming VHDL descriptions into formal component-based models 将VHDL描述转换为正式的基于组件的模型

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990320

Ayoub Nouri, Rahma Ben Atitallah, A. Molnos, Christian Fabre, Frédéric Heitzmann, O. Debicki

引用次数: 0