RapidSoC: short turnaround creation of FPGA based SoCs

Jakob Wenzel, C. Hochberger
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引用次数: 4

Abstract

Field Programmable Gate Arrays (FPGA) offer the opportunity to build individual hardware solutions even for applications which are produced in small quantity. Quite often, these customized Systems-on-Chip (SoC) contain soft-core processors and a selection of standard peripherals. Synthesizing such systems can be time consuming and thus, design space exploration can become a rather long process. In this contribution, we show an approach to substantially speed up the time to create such system implementations. The price for this improved synthesis time is a slightly reduced operating frequency, which is acceptable in many cases. Using a set of benchmark system configurations, we evaluate our approach against state of the art commercial synthesis tools in terms of tool runtime, resource utilization and achieved system clock frequency.
RapidSoC:基于FPGA的soc的短周期创建
现场可编程门阵列(FPGA)提供了构建单个硬件解决方案的机会,即使是少量生产的应用程序。通常,这些定制的片上系统(SoC)包含软核处理器和一系列标准外设。综合这些系统可能很耗时,因此,设计空间探索可能成为一个相当长的过程。在本文中,我们展示了一种大大加快创建此类系统实现时间的方法。这种改进合成时间的代价是稍微降低工作频率,这在许多情况下是可以接受的。使用一组基准系统配置,我们根据工具运行时间、资源利用率和实现的系统时钟频率来评估我们的方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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