Transforming VHDL descriptions into formal component-based models

Abstract

In this work, we investigate a transformation of VHDL descriptions into equivalent formal models. The targeted equivalence is at the level of the functional behavior. That is, we aim at producing formal models that have the same functional simulation behavior as the original VHDL implementation. We rely on the BIP component-based modeling language as the underlying formalism for this transformation. The expected benefits of such a transformation are: enabling the formal verification of hardware designs, allowing for software/hardware system modeling within the same formal framework, and, potentially, accelerating VHDL designs functional simulation by producing distributed BIP models. We show, through a case study, that the transformation is feasible and worth to develop.