2016 International Symposium on Rapid System Prototyping (RSP)最新文献_第2页

Embedded virtualization for the design of secure IoT applications 用于安全物联网应用设计的嵌入式虚拟化

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990301

C. Moratelli, S. J. Filho, M. V. Neves, Fabiano Hessel

引用次数: 21

On-board non-regression test of HLS tools targeting FPGA 针对FPGA的HLS工具的板载非回归测试

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990307

Arief Wicaksana, Adrien Prost-Boucle, O. Muller, F. Rousseau, A. Sasongko

引用次数: 5

EEGu2: an embedded device for brain/body signal acquisition and processing EEGu2:一种用于脑/身体信号采集和处理的嵌入式设备

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990304

Shen Feng, Mian Tang, F. Quivira, Tim Dyson, Filip Cuckov, G. Schirner

{"title":"EEGu2: an embedded device for brain/body signal acquisition and processing","authors":"Shen Feng, Mian Tang, F. Quivira, Tim Dyson, Filip Cuckov, G. Schirner","doi":"10.1145/2990299.2990304","DOIUrl":"https://doi.org/10.1145/2990299.2990304","url":null,"abstract":"Brain/Body Computer Interface (BBCI) technology facilitates research in human cognition and assistive technologies. BBCI acquires and analyzes physiological signals from human body/brain such as electroencephalography (EEG) to observe human physiological states and potentially enable external control. BBCI devices require accurate data acquisition systems with sufficient dynamic range for various brain/body signals. Also, embedded processing is desirable for real-time interaction and flexible deployment. However, most off-the-shelf BBCI devices are very costly, e.g. g.USBamp at $15K and do not offer embedded processing. Hence, an open embedded device for BBCI acquisition and processing is needed to foster the BBCI research. This paper proposes EEGu2 as a portable embedded BBCI device. Based on a BeagleBone Black (BBB), EEGu2 integrates a custom-designed cape including 2 PCBs: an acquisition board for 16-channel 24-bit acquisition up to 1KHz sampling frequency and a power board for wall charging and powering mobile operations. EEGu2 measurement shows a high acquisition accuracy with 25dB signal-to-noise ratio and 0.785μV peak-to-peak input referred noise. At maximum performance, the cape consumes 101.2 mW while BBB consumes 1850 mW. With two lithium batteries, EEGu2 operates independently 12 hours. We demonstrate the flexibility and portability of EEGu2 in the context of Human-in-the-Loop Cyber-Physical Systems (HiLCPS) that augments human interaction with physical world through BBCI. The EEGu2 firmware is integrated into the HiLCPS Framework to enable the location transparent access via the MATLAB interface. EEGu2 empowers rapid embedded BBCI application deployment and we show the flexibility of EEGu2 with a BCI Speller application that acquires real-time EEG signals and infers the user spelling based on Steady State Visually Evoked Potential.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116145474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

MORPh: mobile OLED power friendly camera system MORPh:移动OLED节能相机系统

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990302

Xiang Chen, Jiachen Mao, Kent W. Nixon, Yiran Chen

{"title":"MORPh: mobile OLED power friendly camera system","authors":"Xiang Chen, Jiachen Mao, Kent W. Nixon, Yiran Chen","doi":"10.1145/2990299.2990302","DOIUrl":"https://doi.org/10.1145/2990299.2990302","url":null,"abstract":"With superior advantages of better display quality and power efficiency, the latest OLED technology has achieved unprecedented popularity in the display screen market. However, the OLED remains one of the most power-hungry components in mobile devices. Various optimization schemes have been proposed based on the color-dependent power consumption feature of OLED pixels. These schemes mainly focus on color modification during the playback phase and require significant overhead in terms of frame analysis and real-time modification. While such schemes are effective, the power saving opportunities during the camera recording phase are overlooked. To further enhance the power optimization, the camera parameters during the recording phase could be effectively utilized to reduce or eliminate the optimization overhead. Hence, we proposed MORPh, a cross-layer optimization system for OLED display in the smartphones. We analyze three fundamental parameters of smartphone camera system and their impact on the OLED screen power consumption. We then define corresponding metrics to quantitatively assess each parameter's potential of power saving guidance. Finally, we develop a set of schemes and integrated them into a video recording and playback application on an existing Android smartphone. The experiments results indicate power saving of 7.3% 39.7%, and 20.3% on average while maintaining perceived visual quality.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114833005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Overloads in compositional embedded real-time control systems 复合嵌入式实时控制系统中的过载

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990309

Akramul Azim

{"title":"Overloads in compositional embedded real-time control systems","authors":"Akramul Azim","doi":"10.1145/2990299.2990309","DOIUrl":"https://doi.org/10.1145/2990299.2990309","url":null,"abstract":"Component-based design is important for the design of complex embedded software. By properly defining component interfaces, new components can be formed by composing existing components. A newly formed component may be further composed of other components. One of the key requirements for guaranteeing the compositionality of components in real-time systems is that the composite model must be consistent with, and indistinguishable from, the interface of a primitive component so that all real-time requirements are met. In addition to being used widely for schedulability analysis on different techniques such as earliest deadline first (EDF) and rate monotonic (RM), supply-demand functions have been applied to perform compositional schedulability analysis with periodic resource models. However, supply-demand function analysis for compositional schedules has only been done for hard real-time systems guarantees. This work analyzes overloads in embedded real-time control systems with soft deadlines and the analysis helps to build a compositional system that can tolerate delays. This paper also associates the schedulability analysis with a control application using a rapid prototype implementation.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130991205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Simulation driven insertion of data prefetching instructions for early software-on-SoC optimization 模拟驱动的数据预取指令插入，用于早期的soc软件优化

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990315

P. N. Ntafam, E. Paire, A. Clouard, F. Pétrot

{"title":"Simulation driven insertion of data prefetching instructions for early software-on-SoC optimization","authors":"P. N. Ntafam, E. Paire, A. Clouard, F. Pétrot","doi":"10.1145/2990299.2990315","DOIUrl":"https://doi.org/10.1145/2990299.2990315","url":null,"abstract":"A System-On-Chip (SoC) is a combination of hardware and software which interact to perform a set of functions, usually for some specific application domain. However, with the increasing complexity of both hardware and software, estimating and optimizing the performance of software on SoC during the design process is becoming a difficult objective. The aim of this paper is to show that observability provided by cycle accurate (CA) simulations using virtual platforms available early in the design flow is helping to obtain estimations and to design a software strategy which optimizes software-on-SoC performance, based on some particular metrics. We apply this approach to a case study which tackles the memory wall problem and contributes to its resolution by using software data prefetching technique. We exploit profiling capabilities provided by simulation models, by analyzing the collected data to identify high memory accesses latencies and finally inserting data prefetching instructions in a suitable and non-intuitive way for increasing system execution performance. Bubble sort is used as experimental methodology and the Inverse Discrete Cosine Transform (JPEG IDCT) routine typical from an industrial decoder is used as initial case study. Based on platform simulation observability, we reach an improvement of more than 25% on the overall execution time.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127250112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of an expandable real-time simulation (eRTS) platform for multi-level rapid prototyping 多级快速成型可扩展实时仿真(eRTS)平台设计

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990311

Ankurkumar Patel, T. Silloway, Fnu Qinggele, Yong-Kyu Jung

{"title":"Design of an expandable real-time simulation (eRTS) platform for multi-level rapid prototyping","authors":"Ankurkumar Patel, T. Silloway, Fnu Qinggele, Yong-Kyu Jung","doi":"10.1145/2990299.2990311","DOIUrl":"https://doi.org/10.1145/2990299.2990311","url":null,"abstract":"A real-time simulation (RTS) platform is a critical design and verification for rapidly designing and testing electrical and computing hardware as well as embedded software employed in real-time embedded applications, including an autonomous electric vehicle (AEV). We have developed a wirelessly expandable real-time simulation (eRTS) platform for mixed-level rapid prototyping of an AEV system. The eRTS platform consisting of a microkernel-based multi-core RTS and multiple monolithic-kernel console units is interoperable to FPGA-based virtual prototypes and further expandable to the real prototype via wireless (IEEE 802.15.4). The multi-core RTS and multi-console units are interfaced with high-speed wire/wireless (IEEE 802.3u/802.11g) for both software-/hardware-in-the-loops (SIL/HIL) simulations. In particular, the eRTS provides a mixedlevel of intuitively expandable HIL simulations with software models and virtual/real prototypes. The proposed eRTS platform swiftly handles different scale and complexity of AEV testing at various development stages while satisfying real-time constraints (i.e., 7 μs resolutions and 0.3% HIL simulation error) of the AEV software models and virtual/real prototypes.","PeriodicalId":407053,"journal":{"name":"2016 International Symposium on Rapid System Prototyping (RSP)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122109809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Model-driven design & synthesis of the SHA-256 cryptographic hash function in rewire rewire中SHA-256加密哈希函数的模型驱动设计与合成

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990318

W. Harrison, A. Procter, G. Allwein

引用次数: 4

On platforms for CPS - adaptive, predictable and efficient 在平台上的CPS -自适应，可预测和高效

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990308

L. Thiele, Felix Sutton, Romain Jacob, R. Lim, Reto Da Forno, J. Beutel

引用次数: 2

Architectural performance analysis of FPGA synthesized LEON processors FPGA合成LEON处理器体系结构性能分析

2016 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2016-10-01 DOI: 10.1145/2990299.2990306

C. Damman, G. Edison, F. Guet, É. Noulard, L. Santinelli, J. Hugues

引用次数: 4