Inter-FPGA routing environment for performance exploration of multi-FPGA systems

Abstract

Multi-FPGA platforms are a popular choice today for complex system prototyping because they offer high execution speed, low cost, and real world testing experience. However, performance of multi-FPGA based systems is severely affected by widening logic to I/O gap in FPGAs. In order to address the performance issue, in this work, we propose an exploration and optimization flow for multi-FPGA based prototyping that gives an end-to-end experience starting from benchmark generation to optimized inter- FPGA routing. Using generic tools of the flow, ten large benchmarks are generated. Then, through a generic novel inter-FPGA routing environment, effect of variation of number of FPGAs as well as number of inter-FPGA tracks on the performance of a target design is explored. For performance exploration and optimization, five different FPGA boards are utilized where number of FPGAs on board are varied from two to six. Moreover, for each board four different inter-FPGA track combinations are used. Experimental results reveal that multi-FPGA boards with inter-FPGA tracks corresponding optimally to the cut net requirements of benchmarks under consideration give best frequency results. Furthermore, frequency comparison between different boards shows that FPGA board with six FPGAs gives, on average, best frequency results. Finally, we also perform frequency-price analysis which shows that board with four FPGAs gives better frequency-price tradeoff as compared to other FPGA boards under consideration.