Automatic detection and elision of reset sub-circuits

Abstract

Electronic circuits are too complex to be designed by hand so hardware languages, like Verilog, and Computer Aided Design (CAD) tools are used for these purposes. Two main types of circuits are Application-Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). ASICs require a reset sub-circuit to initialize their state; however, such a procedure is not necessary for FPGAs that support power-on reset. We propose and evaluate a tool that automatically detects and elides reset sub-circuits as part of the Verilog-to-Routing (VTR) CAD flow and in particular Odin II. Also, our tool can be used to decide if a reset sub-circuit has been properly implemented and can point towards memory components that have not been initialized. Such a tool is the first to our knowledge. Our tests with the VTR Verilog benchmarks and other Verilog circuits showed significant reductions in resource consumption on the target FPGAs as much as 25.9% shorter critical path, 90.39% shorter maximum net, 62.84% fewer used logic blocks and 30.87% fewer used routing elements. Also, our approach yielded significant reductions in the execution time of the placement-and-routing algorithm for the elided circuits that were as high as 4.5 times faster VPR execution and 3.35 times faster overall VTR flow execution.