2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献_第8页

Multi-tasking and Memcomputing with Memristor Cellular Nonlinear Networks 基于忆阻器细胞非线性网络的多任务和Memcomputing

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294882

I. Messaris, A. Ascoli, A. S. Demirkol, R. Tetzlaff, L. Chua

引用次数: 2

A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC 奈奎斯特DAC的宽带六阶可编程带通DEM实现

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294912

S. Mehta, Brendan Mullane, Vincent O’Brien, R. Pelliconi, C. Erdmann

引用次数: 0

An Untrimmed 14-bit Non-Binary SAR-ADC Using 0.37 fF-Capacitors in 180 nm for 1.1 µW at 4 kS/s 一种未经修整的14位非二进制SAR-ADC，采用0.37 ff电容，在180 nm波长下，在4ks /s下输出1.1µW

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294971

S. Schmickl, Thomas Faseth, H. Pretl

引用次数: 4

A Tile-based Fused-layer CNN Accelerator for FPGAs 基于tile的fpga融合层CNN加速器

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294981

Fabrizio Indirli, Ahmet Erdem, C. Silvano

{"title":"A Tile-based Fused-layer CNN Accelerator for FPGAs","authors":"Fabrizio Indirli, Ahmet Erdem, C. Silvano","doi":"10.1109/ICECS49266.2020.9294981","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294981","url":null,"abstract":"The acceleration of Convolutional Neural Networks (CNNs) on FPGAs is becoming increasingly popular for computer vision tasks. However, the limited memory and bandwidth of these devices pose some challenges to the design of conventional CNN accelerators, which use external DRAM to store the intermediate results of each layer. To mitigate these criticalities, researchers have proposed the fused-layer methodology, which diminishes the accesses to the external DRAM by accelerating simultaneously multiple subsequent layers on the same chip. In this work, we propose a configurable fused-layer accelerator that exploits output tiling and the half-precision float datatype to reduce resource utilization. We assessed its effectiveness with experiments on VGG-16 and Yolo-Lite CNNs, targeting a Xilinx Zynq ZU6EG FPGA. Our design achieved up to 42% speedup and up to 95% fewer transfers from external memory compared to a single-layer baseline solution. Moreover, to ease and quicken the design space exploration, we developed a Machine Learning model that predicts the performance and the resource utilization of our accelerator with an accuracy > 90% on the reported dataset.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Tiny Two-Stage 1-GHz Time-Difference Amplifier Without Input Time-Difference Limitation and Extreme Points 无输入时差限制和极值点的微型两级1 ghz差分放大器

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294917

Atsushi Mamba, M. Sasaki

{"title":"Tiny Two-Stage 1-GHz Time-Difference Amplifier Without Input Time-Difference Limitation and Extreme Points","authors":"Atsushi Mamba, M. Sasaki","doi":"10.1109/ICECS49266.2020.9294917","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294917","url":null,"abstract":"Conventional time-difference amplifiers (TDAs), which can improve the time-domain resolution, use capacitors and an external control circuit to make gain, control gain, and improve linearity. However, this configuration produces a limitation in the maximum operating frequency and high power consumption. This paper proposes and demonstrates a TDA for a variety of time-domain circuits. The proposed TDA consists of two circuits, including a modified SR latch circuit and gain control circuit (GCC). The linearity of this TDA is controlled by the GCC, which is a part of the amplifier, by only using the time-difference signals generated by the modified SR latch. This TDA is fabricated in the 0.18 J.1m CMOS process, and the core area occupies only 13 µm×14 µm. The measurement results show that the output time difference monotonically increases and has no extreme points for an entire clock period with a 1-GHz input clock. The gain of the flat region in the range of ±130 ps is 1.54 with a maximum gain error of less than 6.5%, and the power consumption is 2230 µW. The proposed TDA can be used for not only a time to digital converter, similar with conventional TDAs, but also circuits using the time domain, such as a high-speed comparators and time-difference adjustment methods.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"2028 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127464609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Compact CMOS Class-AB Output Stage With Robust Behavior Against PVT Variations 具有抗PVT变化鲁棒行为的紧凑CMOS ab级输出级

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294975

Ó. Pereira-Rial, P. López, R. Pérez-Aloe, J. M. Carrillo, J. F. Duque-Carrillo

引用次数: 0

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination 探索NLMS和IPNLMS自适应滤波VLSI硬件架构用于鲁棒脑电信号伪影消除

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294785

A. Rosa, Patrícia Ücker, Guilherme Paim, E. Costa, S. Almeida, S. Bampi

{"title":"Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination","authors":"A. Rosa, Patrícia Ücker, Guilherme Paim, E. Costa, S. Almeida, S. Bampi","doi":"10.1109/ICECS49266.2020.9294785","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294785","url":null,"abstract":"The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. Embedded systems require low circuit area (cost) and efficient hardware architectures. Adaptive filtering plays a vital role as a single method and hybrid approaches for robustly eliminating the noise of the real-world EEG measures. In this paper, we propose and implement hardware architectures for both NLMS and IPNLMS adaptive filters. We investigate the filtering performance and circuit area, timing, and power dissipation of the hardware architecture proposals. To leverage the power-efficiency, we improve our hardware architectures employing the data-gating circuit design technique, which provided up to 20% power savings. Also, applying an HDL-Simulink co-simulation, we perform the hardware architectures tradeoff comparing the synthesis results and filtering performance. Our investigation demonstrates that IPNLMS reduces the time domain error in 11%, increasing less than 1% of circuit area and about the double of the energy per operation, compared to the NLMS.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114969143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improvements on the Design of the Low Saturation Onset Transistor 低饱和起始晶体管设计的改进

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294977

Eliana Silva dos Santos, F. Andrade, M. D. Pereira, A. Cunha

引用次数: 1

A Design of Cold Start Charge Pump for Flexible Thermoelectric Generator with High Output Impedance 高输出阻抗柔性热电发电机冷启动电荷泵设计

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294857

Kazuma Koketsu, T. Tanzawa

{"title":"A Design of Cold Start Charge Pump for Flexible Thermoelectric Generator with High Output Impedance","authors":"Kazuma Koketsu, T. Tanzawa","doi":"10.1109/ICECS49266.2020.9294857","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294857","url":null,"abstract":"This paper proposes a practical control circuit design of power converter for energy transducer with high output impedance. In conventional control circuit systems, the input voltage of the power converter is set so that the output power becomes maximum. However, this operating point voltage can be lower than the lower limit of the supply voltage at which the power converter can work. The proposed control circuit enables the power converter to operate when the output voltage is lower than a target voltage Vpp and the input voltage is higher than a specified voltage VDD. As a result, the input impedance ZCPin of the power converter can be low enough to extract power from the energy transducer via a power supply capacitor CDD when the power converter is enabled. On the other hand, ZCPin can be high enough to charge up CDD via the energy transducer when the power converter is disabled. As a result, 1) the operating point of the input voltage can be controlled to be higher than the minimum supply voltage, 2) a maximum power can be extracted, and 3) the output voltage is controlled to be the target voltage. The proposed circuit system was fabricated in 65nm 1V CMOS and its operation was verified. The proposed integrated circuit converts an output power of 50µW at an output voltage of 2.5V from a thermoelectric energy transducer with an open circuit voltage of 0.9V and an output impedance of 400Ω.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125723965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Newcastle Visual Prosthesis Implantable Control Unit 纽卡斯尔视觉假体植入式控制单元

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294853

Yu Liu, Nabeel Fattah, P. Degenaar

引用次数: 1