2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献

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Advanced Transitive-Closure-Graph-Based Placement Representation for Analog Layout Design 基于传递闭图的模拟布局设计的高级布局表示
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294968
Lian He, Zhenxin Zhao, Y. Chen, Lihong Zhang
{"title":"Advanced Transitive-Closure-Graph-Based Placement Representation for Analog Layout Design","authors":"Lian He, Zhenxin Zhao, Y. Chen, Lihong Zhang","doi":"10.1109/ICECS49266.2020.9294968","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294968","url":null,"abstract":"Due to complexity and susceptibility of analog layouts, maturity state of analog physical design automation has largely lagged behind that of the digital counterpart. It demands effective placement representations to handle nontrivial analog placement topologies especially in the advanced nanometer technologies. In this paper, we propose an advanced transitive-closure-graph-based placement representation (ATCG) to effectively and efficiently deal with analog placement. The versatility and flexibility of ATCG can ensure it to accurately control spacing and merging constraints uniquely required by analog layout design. Moreover, we also present a redundancy control scheme among the representation states in order to generate high-performance analog placement with high computation efficiency. Our experimental results demonstrate high efficacy of our proposed representation.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134303956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast Intra Mode Decision for 3D-HEVC Depth Map Coding using Decision Trees 快速模式内决策的3D-HEVC深度图编码使用决策树
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294919
Christopher Moura, Mário Saldanha, G. Sanchez, C. Marcon, M. Porto, L. Agostini
{"title":"Fast Intra Mode Decision for 3D-HEVC Depth Map Coding using Decision Trees","authors":"Christopher Moura, Mário Saldanha, G. Sanchez, C. Marcon, M. Porto, L. Agostini","doi":"10.1109/ICECS49266.2020.9294919","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294919","url":null,"abstract":"This paper presents a fast intra mode decision for depth map coding on 3D-High Efficiency Video Coding (3D-HEVC) based on decision trees. The proposed solution uses data mining and machine learning to correlate the encoder context attributes and build a set of decision trees. Each decision tree defines if a depth map block must be or not be evaluated by the Depth Modeling Modes (DMMs), considering the encoding context. The decision trees were trained using data extracted from the 3D-HEVC Test Model (3D-HTM) under all-intra encoder configuration. The proposed solution was evaluated according to the Common Test Conditions (CTC), reducing 50.2% the execution time of the depth map coding, and impacting only 0.07% in the Bjontegaard Delta BitRate (BDBR) of the synthesized views.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133012085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Power Memristor-Based Shift Register Design 基于低功耗忆阻器的移位寄存器设计
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294907
A. Sasi, M. Ahmadi, A. Ahmadi
{"title":"Low Power Memristor-Based Shift Register Design","authors":"A. Sasi, M. Ahmadi, A. Ahmadi","doi":"10.1109/ICECS49266.2020.9294907","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294907","url":null,"abstract":"The use of memristors is considered to be an appropriate alternative solution to Complementary Metal Oxide Semiconductor (CMOS) technology's scaling limitation. In digital design, shift registers are widely used and considered to be basic memory devices. In this paper, a fast and efficient area memristor-only-based shift register, as well as a hybrid CMOS/memristor-based shift register are proposed. Specifically, a 4-bit shift register with only 8 memristor devices and a hybrid CMOS /memristor with 64 memristor devices and 64 CMOS transistors were implemented and simulated using Cadence Virtuoso. The simulation results demonstrate the design's efficient functionality. Compared to the implementation of a CMOS-memristor based shift register, the implementation of the proposed design is more efficient when concerning area and speed with respect to the implementation of the Memristor Based-Material-Implication (IMPLY) memristive shift register. In addition, the shift register with only memristor-based has a significant power reduction of over 30% compared to a CMOS design shift register.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133347121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of analog and mixed circuits for resonator's Q-factor measurement 谐振器q因子测量模拟与混合电路的设计
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294784
Ming Zhang, N. Llaser
{"title":"Design of analog and mixed circuits for resonator's Q-factor measurement","authors":"Ming Zhang, N. Llaser","doi":"10.1109/ICECS49266.2020.9294784","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294784","url":null,"abstract":"In this paper, a review of a resonator's quality factor (Q-factor) measurement is given. The presentation is based on a general Q-factor measurement system so that one can have an overview of such a measurement system: from excitation of a resonator to acquisition of signal resulting from the vibration of the resonator till the signal processing to get the Q-factor. From the way in which the excitation and the acquisition are performed, as well as the way in which the signal is processed, three major approaches can be distinguished: frequency domain, time-frequency domain and time domain. An overview of the advantages and the limitations of each approach is given with a focus on time domain measurement for it offers the only way to conduct an in-situ Q-factor measurement. Two time-domain design examples are also illustrated.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133846142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Cost Production of 3D Printed Lab-on Chip (LOC) Device for Oil-in-Water Emulsion Separation 低成本生产的3D打印实验室芯片(LOC)装置用于油包水乳液分离
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294860
Amr A.M. Elrouby, Ahmed Ali, Ahmed A. R. Abdel-Aty, Abdelhamid M. Abu-Elnaga, A. Khalil
{"title":"Low-Cost Production of 3D Printed Lab-on Chip (LOC) Device for Oil-in-Water Emulsion Separation","authors":"Amr A.M. Elrouby, Ahmed Ali, Ahmed A. R. Abdel-Aty, Abdelhamid M. Abu-Elnaga, A. Khalil","doi":"10.1109/ICECS49266.2020.9294860","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294860","url":null,"abstract":"High concentration of oil and grease produced from gas and oil industries have been considered as a crucial problem facing aquatic ecosystems. Therefore, the development of functional materials for efficient removal of oil from oil/water emulsion is imperative. In the current study, a low cost and highly efficient 3D printed lab-on chip (LOC) device is presented. Firstly, the device model was designed and printed using stereolithography (SLA) 3D printing as two parts connected using screws and bolts. Secondly, isotropic, and anisotropic PES membranes were prepared by induced phase separation method and integrated in the device. The fabricated membranes were characterized in terms of morphology, porosity, pore size and hydrophilicity. The results revealed that drastic changes in the membrane morphology and overall structure were achieved by using vapour induced phase separation instead of the traditional phase separation method. It is noticeable that the isotropic membrane has higher permeability and oil rejection compared to the anisotropic one. The current study introduces a proof of concept of compact and integrated membrane-based LOC for treatment of small volumes of oily wastewater.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"157 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114002201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGA DeepHLS:一个完整的工具链,用于自动合成深度神经网络到FPGA
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294881
M. Riazati, M. Daneshtalab, Mikael Sjödin, B. Lisper
{"title":"DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGA","authors":"M. Riazati, M. Daneshtalab, Mikael Sjödin, B. Lisper","doi":"10.1109/ICECS49266.2020.9294881","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294881","url":null,"abstract":"Deep neural networks (DNN) have achieved quality results in various applications of computer vision, especially in image classification problems. DNNs are computational intensive, and nowadays, their acceleration on the FPGA has received much attention. Many methods to accelerate DNNs have been proposed. Despite their performance features like acceptable accuracy or low latency, their use is not widely accepted by software designers who usually do not have enough knowledge of the hardware details of the proposed accelerators. HLS tools are the major promising tools that can act as a bridge between software designers and hardware implementation. However, not only most HLS tools just support C and C++ descriptions as input, but also their result is very sensitive to the coding style. It makes it difficult for the software developers to adopt them, as DNNs are mostly described in high-level languages such as Tensorflow or Keras. In this paper, an integrated toolchain is presented that, in addition to converting the Keras DNN descriptions to a simple, flat, and synthesizable C output, provides other features such as accuracy verification, C level knobs to easily change the data types from floating-point to fixed-point with arbitrary bit width, and latency and area utilization adjustment using HLS knobs.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"18 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114045455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing 一种高效的基于nlms的VLSI结构,用于稳健的feg提取和FHR处理
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294943
Patrícia U. L. da Costa, Guilherme Paim, L. G. Rocha, E. Costa, S. Almeida, S. Bampi
{"title":"An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing","authors":"Patrícia U. L. da Costa, Guilherme Paim, L. G. Rocha, E. Costa, S. Almeida, S. Bampi","doi":"10.1109/ICECS49266.2020.9294943","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294943","url":null,"abstract":"This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122831572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 250-ps Integrated Ultra-Wideband Timed Array Beamforming Receiver in 0.18 μm CMOS 基于0.18 μm CMOS的250-ps集成超宽带定时阵列波束成形接收器
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294795
S. R. Aghazadeh, H. Martínez, X. Aragonès, A. Saberkari
{"title":"A 250-ps Integrated Ultra-Wideband Timed Array Beamforming Receiver in 0.18 μm CMOS","authors":"S. R. Aghazadeh, H. Martínez, X. Aragonès, A. Saberkari","doi":"10.1109/ICECS49266.2020.9294795","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294795","url":null,"abstract":"This paper presents a 4-channel ultra-wideband (UWB) timed array beamforming receiver designed in a standard 0.18-μm CMOS technology. The proposed timed array receiver achieves a maximum delay of 250 ps at the maximum beam steering angle of ±42° with 10.5° (8 steps) steering resolution and 2-cm antenna spacing. Each receiver channel provides gains ranging from 3.6 to −35 dB and less than 8% delay variation for all delay settings over a 3.1−10.6-GHz frequency range, while consuming a maximum of 58 mW power from a 1.8-V supply. The average −1-dB compression point PldBis −9.9 dBm. The proposed architecture is modeled and simulated by using Virtuoso Cadence.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124004581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC) 基于低抖动双尾强臂锁存器的数字时间转换器
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294801
Zeeshan Ali, R. MakwanaHarshit, Shalabh Gupta
{"title":"A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC)","authors":"Zeeshan Ali, R. MakwanaHarshit, Shalabh Gupta","doi":"10.1109/ICECS49266.2020.9294801","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294801","url":null,"abstract":"Digital to time converters (DTCs) have recently become important in phase comparison path in low jitter fractional-$N$ phase-locked loops (PLLs). This paper proposes a simple technique to implement a DTC using the Schmitt trigger. The proposed DTC consists of a double-tailed Strong-Arm latch that acts as a comparator, unlike other DTCs that involve inverters as a comparator. A compression logic is designed inside digital to analog converter (DAC) to improve the DTC linearity. By changing the DAC output voltage, using a control word, the required amount of delay can be added to the reference signal. The proposed 10-bit double-tailed Strong-Arm latch based DTC has been designed in 65 nm CMOS technology. A resolution of 380 fs, an integral non-linearity (INL) of 1.7 ps and RMS jitter of 0.2 ps with 2.5 mW power consumption at 100MHz, have been achieved, which shows the best FoMjitter in 65 nm technology.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124052501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Formal Verification Approach for Detecting Opcode Trojans 一种检测操作码木马的形式化验证方法
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294803
Nimish Mathure, S. Srinivasan, Kushal K. Ponugoti, Akansha Malik, Samuel Quanbeck
{"title":"A Formal Verification Approach for Detecting Opcode Trojans","authors":"Nimish Mathure, S. Srinivasan, Kushal K. Ponugoti, Akansha Malik, Samuel Quanbeck","doi":"10.1109/ICECS49266.2020.9294803","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294803","url":null,"abstract":"Hardware Trojans are malicious circuit modifications and are a rising threat to the integrated circuit supply chain. There are a number of trojans directed specifically at microprocessor designs. This paper examines the threat of invalid opcodes being used as trigger mechanism for trojans in microprocessors. We demonstrate the effect of such trojans and propose an automated formal verification methodology to detect such trojans. The methodology was tested on processor models based on MIPS and RISC-V architecture. Processor benchmark circuits with as many as 400,000 gates were verified using our approach.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121374258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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