2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献_第3页

Real-Time Trainable Data Converters for General Purpose Applications 用于通用应用的实时可训练数据转换器

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232209

Loai Danial, Shahar Kvatinsky

引用次数: 3

Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices 石墨烯量子点接触器件上的多值逻辑电路

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232214

K. Rallis, G. Sirakoulis, I. Karafyllidis, A. Rubio

引用次数: 6

Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies 新兴中介技术低摆幅信号的能源效率

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232203

E. Maragkoudaki, P. Mroszczyk, V. Pavlidis

{"title":"Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies","authors":"E. Maragkoudaki, P. Mroszczyk, V. Pavlidis","doi":"10.1145/3232195.3232203","DOIUrl":"https://doi.org/10.1145/3232195.3232203","url":null,"abstract":"Interconnects often constitute the major bottleneck in the design process of low power integrated circuits (IC). Although 2.5-D integration technologies support physical proximity, the dissipated power in the communication links remains high. In this work, the additional power savings for interposer-based interconnects enabled by low swing signaling is investigated. The energy consumed by a low swing scheme is, therefore, compared with a full swing solution and the critical length of the interconnect, above which the low swing solution starts to pay off, is determined for diverse interposer technologies. The energy consumption is compared for three different substrate materials, silicon, glass, and organic. Results indicate that the higher the load capacitance of the communication medium is, the greater the energy savings of the low swing circuit are. Specifically, in cases that electrostatic discharge (ESD) protection is required, the low swing circuit is always superior in terms of energy consumption due to the high capacitive load of the ESD circuit, regardless the substrate material and the link length. Without ESD protection, the highest critical length is about 380 μm for glass and organic interposers. To further explore the limits of power reduction from low swing signaling for 2.5-D ICs, the effect of typical interconnect parameters such as width and space on the energy efficiency of low swing communication is evaluated.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130897075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrated Synthesis Methodology for Crossbar Arrays 交叉杆阵列的集成综合方法

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232211

Muhammed Ceylan Morgül, O. Tunali, M. Altun, L. Frontini, V. Ciriani, E. Vatajelu, L. Anghel, C. A. Moritz, M. Stan, D. Alexandrescu

引用次数: 7

An Aging Resilient Neural Network Architecture 一个老化的弹性神经网络架构

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232208

S. Mozaffari, K. Gnawali, S. Tragoudas

引用次数: 8

Complementary Arranged Graphene Nanoribbon-based Boolean Gates 互补排列石墨烯纳米带布尔门

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232199

Yande Jiang, N. C. Laurenciu, S. Cotofana

{"title":"Complementary Arranged Graphene Nanoribbon-based Boolean Gates","authors":"Yande Jiang, N. C. Laurenciu, S. Cotofana","doi":"10.1145/3232195.3232199","DOIUrl":"https://doi.org/10.1145/3232195.3232199","url":null,"abstract":"With CMOS feature size heading towards atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanorib-bons (GNRs), owing to graphene’s excellent electronic properties, may serve as basic blocks for carbon-based nanoelectronics. In this paper we build upon the fact that GNR behaviour can be controlled according to some desired functionality via top/back gate contacts and propose to combine GNRs with complementary functionalities to construct Boolean gates. To this end, we introduce a generic GNR-based Boolean gate structure, composed of two GNRs, i.e., a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the inverted Boolean function. Subsequently, by properly adjusting GNRs’ dimensions and topology, we design 2-input AND, NAND, and XOR graphene-based Boolean gates, as well as 1-input gates, i.e., inverter and buffer. Our SPICE simulations indicate that the proposed gates exhibit a smaller propagation delay, from 23% for the XOR gate to 6× for the AND gate, and 2 orders of magnitude smaller power consumption, when compared with 7 nm CMOS based counterparts, while requiring a 1 to 2 orders of magnitude smaller active area footprint. These results clearly indicate that GNR-based gates have great potential as basic building blocks for future beyond CMOS energy effective nanoscale circuits.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125046081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits 基于串扰的多态电路细粒度重构技术

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-04 DOI: 10.1145/3232195.3232227

Naveen Kumar Macha, Sandeep Geedipally, Bhavana Tejaswini Repalle, Md Arif Iqbal, Wafi Danesh, Mostafizur Rahman

{"title":"Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits","authors":"Naveen Kumar Macha, Sandeep Geedipally, Bhavana Tejaswini Repalle, Md Arif Iqbal, Wafi Danesh, Mostafizur Rahman","doi":"10.1145/3232195.3232227","DOIUrl":"https://doi.org/10.1145/3232195.3232227","url":null,"abstract":"Truly polymorphic circuits, whose functionality/circuit behavior can be altered using a control variable, can provide tremendous benefits in multi-functional system design and resource sharing. For secure and fault tolerant hardware designs these can be crucial as well. Polymorphic circuits work in literature so far either rely on environmental parameters such as temperature, variation etc. or on special devices such as ambipolar FET, configurable magnetic devices, etc., that often result in inefficiencies in performance and/or realization. In this paper, we introduce a novel polymorphic circuit design approach where deterministic interference between nano-metal lines is leveraged for logic computing and configuration. For computing, the proposed approach relies on nano-metal lines, their interference and commonly used FETs. For polymorphism, it requires only an extra metal line that carries the control signal. In this paper, we show a wide range of crosstalk polymorphic logic gates and their evaluation results. We also show an example of a large circuit that performs both the functionalities of multiplier and sorter depending on the configuration signal. A comparison is made with respect to other existing approaches in literature, and transistor count is benchmarked. For crosstalk-polymorphic circuits, the transistor count reduction range from 25% to 83% with respect to various other approaches. For example, polymorphic AOI21-OA21 cell show 83%, 85% and 50% transistor count reduction, and Multiplier-Sorter circuit show 40%, 36% and 28% transistor count reduction with respect to CMOS, genetically evolved, and ambipolar transistor based polymorphic circuits, respectively.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130065564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Power Analysis of an mRNA-Ribosome System mrna -核糖体系统的功率分析

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-06-21 DOI: 10.1145/3232195.3232223

P. Chatterjee, P. Ghosal

{"title":"Power Analysis of an mRNA-Ribosome System","authors":"P. Chatterjee, P. Ghosal","doi":"10.1145/3232195.3232223","DOIUrl":"https://doi.org/10.1145/3232195.3232223","url":null,"abstract":"Energy is the heart to drive any device, such as any machine. As researchers have been trying to perform low energy operations more and more, energy requirements are turning out to be one of the key features in measuring the performance of a device. On the other hand, as conventional silicon-based computing is approaching a barrier, needs of non-conventional computing is increasing. Though several such computing platforms have arisen to prove itself as a suitable alternative to silicon-based computing, less energy requirement is certainly one of the most sought features in the competition among the new platforms. Moreover, there are certain scenarios where performing calculations in pure bio-molecular ways are highly desired. Although DNA computing has already flagged the success of bio-molecular computing in terms of energy/power requirements, its manual nature keeps it behind from other computing techniques. Another new bio-molecular computing technique Ribosomal Computing, though still in infancy, has shown real promises due to its inherent automation. This work performs an analysis of the energy/power requirements of this computing technique. With the promising result obtained, ribosomal computing can claim itself as a promising computing technique, if combined with its inherent automation.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129539394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution 在容错量子电路中控制蒸馏厂:问题陈述和解决方案分析

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-06-19 DOI: 10.1145/3232195.3232224

A. Paler

{"title":"Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution","authors":"A. Paler","doi":"10.1145/3232195.3232224","DOIUrl":"https://doi.org/10.1145/3232195.3232224","url":null,"abstract":"The failure susceptibility of the quantum hardware will force quantum computers to execute fault-tolerant quantum circuits. These circuits are based on quantum error correcting codes, and there is increasing evidence that one of the most practical choices is the surface code. Design methodologies of surface code based quantum circuits were focused on the layout of such circuits without emphasizing the reduced availability of hardware and its effect on the execution time. Circuit layout has not been investigated for practical scenarios, and the problem presented herein was neglected until now. For achieving fault-tolerance and implementing surface code based computations, a significant amount of computing resources (hardware and time) are necessary for preparing special quantum states in a procedure called distillation. This work introduces the problem of how distilleries (circuit portions responsible for state distillation) influence the layout of surface code protected quantum circuits, and analyses the trade-offs for reducing the resources necessary for executing the circuits. A first algorithmic solution is presented, implemented and evaluated for addition quantum circuits.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130523046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6