2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献

A Recursive Growing & Featuring Mechanism for Nanocomputing Structures 纳米计算结构的递归生长与特征机制

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232215

M. Malita, G. Stefan

引用次数: 0

A Novel Analog to Digital Conversion Concept with Crosstalk Computing 基于串扰计算的新型模数转换概念

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232228

Rajanikanth Desh, Naveen Kumar Macha, Sehtab Hossain, Repalle Bhavana Tejaswini, Mostafizur Rahman

{"title":"A Novel Analog to Digital Conversion Concept with Crosstalk Computing","authors":"Rajanikanth Desh, Naveen Kumar Macha, Sehtab Hossain, Repalle Bhavana Tejaswini, Mostafizur Rahman","doi":"10.1145/3232195.3232228","DOIUrl":"https://doi.org/10.1145/3232195.3232228","url":null,"abstract":"Analog to Digital Converters (ADCs) is the core component of computing systems forming a link between the external stimuli and digital microprocessor operations. Current CMOS based fast ADCs are difficult to scale due to the reliance on transistor sizing and high voltage operations. They also suffer from high power consumption. In this paper, we introduce a novel ADC design which uses the deterministic signal interference between metal lines as a mechanism for signal conversion. In contrast to CMOS ADCs, our approach uses a simple crosstalk tree network of metal lines to convert sampled analog levels to digital code. Here, the sampled analog signal is passed through an input metal line which is capacitively coupled to a series of metal lines in a tree-like layout, and the coupled voltages on the edge of the tree (the leaves) determine the output. The resolution is dependent on the number of branches. We show 2-bit and 3-bit ADC implemented through this mechanism at 16n technology node. Our results indicate the possibility of huge power savings with Crosstalk ADCs in comparison to CMOS; for 2-bit and 3-bit ADCs the power consumption was found to be 43.51μW and 96.74μW respectively at 50M Hz sampling frequency.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"36 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126601029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCube™ Technology 高效节能的4T SRAM Bitcell，具有2T读取端口，适用于28纳米3D单片CoolCube™技术的超低电压操作

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232210

R. Boumchedda, J. Noel, B. Giraud, A. Makosiej, M. Rios, E. Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, D. Turgis, E. Beigné

{"title":"Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCube™ Technology","authors":"R. Boumchedda, J. Noel, B. Giraud, A. Makosiej, M. Rios, E. Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, D. Turgis, E. Beigné","doi":"10.1145/3232195.3232210","DOIUrl":"https://doi.org/10.1145/3232195.3232210","url":null,"abstract":"This paper presents a 4T-based SRAM bitcell optimized both for write and read operations at ultra-low voltage (ULV). The proposed bitcell is designed to respond to the requirements of energy constrained systems, as in the case of most IoT-oriented circuits and applications. The use of 3D CoolCube™ technology enables the design of a stable 4T SRAM bitcell by using data-dependent back biasing. The proposed bitcell architecture provides a major reduction of the write operation energy consumption compared to a conventional 6T bitcell. A dedicated read port coupled to a virtual GND (VGND) ensures a full functionality at ULV of read operations. Simulation results show reliable operations down to 0.35 V close to six sigma (6 σ) without any assist techniques (e.g. negative bitlines), achieving in worst case corner 300 ns and 125 ns in write and read access time, respectively. A 6x energy consumption reduction compared to a ULV ultra-low-leakage (ULL) 6T bitcell is demonstrated.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131380481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices 基于自旋电子器件的稀疏编码算法硬件加速实现

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232220

Deming Zhang, Y. Hou, Chengzhi Wang, Jie Chen, L. Zeng, Weisheng Zhao

{"title":"Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices","authors":"Deming Zhang, Y. Hou, Chengzhi Wang, Jie Chen, L. Zeng, Weisheng Zhao","doi":"10.1145/3232195.3232220","DOIUrl":"https://doi.org/10.1145/3232195.3232220","url":null,"abstract":"In this paper, we explore the possibility of hardware acceleration implementation of sparse coding algorithm with spintronic devices by a series of design optimizations across the architecture, circuit and device. Firstly, a domain wall motion (DWM) based compound spintronic device (CSD) is engineered and modelled, which is envisioned to achieve multiple conductance states. Sequentially, a parallel architecture is presented based on a dense cross-point array of the proposed DWM based CSD, where each dictionary (D) value can be mapped into the conductance of the proposed DWM based CSD at the corresponding cross-point. Benefitting from its massively parallel read and write operation, such proposed parallel architecture can accelerate the selected sparse coding algorithm using a designed dedicated periphery read and write circuit. Experimental results show that the selected sparse coding algorithm can be accelerated by 1400× with the proposed parallel architecture in comparison with software implementation. Moreover, its energy dissipation is 8 orders of magnitude smaller than that with software implementation.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"29 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133752488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Signal Synchronization in Large Scale Quantum-dot Cellular Automata Circuits 大规模量子点元胞自动机电路中的信号同步

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232212

Vassilios A. Mardiris, Orestis Liolis, G. Sirakoulis, I. Karafyllidis

引用次数: 1

Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array 基于可变容差记忆电阻的交叉栅阵列比例逻辑

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232213

M. Escudero, I. Vourkas, A. Rubio, F. Moll

{"title":"Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array","authors":"M. Escudero, I. Vourkas, A. Rubio, F. Moll","doi":"10.1145/3232195.3232213","DOIUrl":"https://doi.org/10.1145/3232195.3232213","url":null,"abstract":"The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications including that of logic circuits. Several memristive logic families have been proposed, each with different attributes, in the current quest for energy-efficient computing systems of the future. However, limited endurance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon an accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and variability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbar-compatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128395763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations 用于逻辑运算的可编程分子-纳米粒子多结网络

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232225

Angelika Balliou, J. Pfleger, G. Skoulatakis, S. Kazim, J. Rakusan, S. Kennou, N. Glezos

引用次数: 1

Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing 基于BDD的内存计算紧凑型忆阻器横条CAD

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232222

Amad Ul Hassen, S. Khokhar, Haseeb Aslam Butt, Sumit Kumar Jha

{"title":"Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing","authors":"Amad Ul Hassen, S. Khokhar, Haseeb Aslam Butt, Sumit Kumar Jha","doi":"10.1145/3232195.3232222","DOIUrl":"https://doi.org/10.1145/3232195.3232222","url":null,"abstract":"The demise of Moore’s law, breakdown of Dennard Scaling, dark silicon phenomenon, process variation, leakage currents and quantum tunneling are some of the hurdles faced in the further advancement of computing systems today. As a result, there is a renewed interest in alternate computing paradigms using emerging nanoelectronic devices. This work uses free binary decision diagrams (FBDDs) for computer-aided design (CAD) of compact memristive crossbars for sneak-path based in-memory computing. The absence of a fixed variable ordering makes FBDDs more compact than their ordered counterpart called reduced ordered binary decision diagrams (ROBDDs). Our design has used the size of the circuit-representation of Boolean functions for selecting different variable orderings along different paths which results in compact FBDDs. We have demonstrated our approach by designing compact crossbars for a four-bit multiplier and other RevLib benchmarks. Our synthesis process yields a 50.1% reduction in area over the previous FBDD-based synthesis for the fourth-output-bit of the multiplier. Overall, our approach has reduced the multiplier area by 20.1%.","PeriodicalId":401010,"journal":{"name":"2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114129922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A Probabilistic Error Model and Framework for Approximate Booth Multipliers 近似展位乘法器的概率误差模型和框架

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232200

Yuying Zhu, Weiqiang Liu, Jie Han, F. Lombardi

引用次数: 2

Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic 基于双层雪崩自旋二极管逻辑的时序电路设计

2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2018-07-17 DOI: 10.1145/3232195.3232221

Vaibhav Vyas, J. Friedman

引用次数: 1