基于串扰计算的新型模数转换概念

Rajanikanth Desh, Naveen Kumar Macha, Sehtab Hossain, Repalle Bhavana Tejaswini, Mostafizur Rahman
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引用次数: 3

摘要

模数转换器(adc)是计算机系统的核心部件,是连接外部刺激和数字微处理器操作的纽带。目前基于CMOS的快速adc由于依赖于晶体管尺寸和高压操作而难以扩展。它们还面临着高功耗的问题。本文介绍了一种利用金属线之间的确定性信号干扰作为信号转换机制的新型ADC设计。与CMOS adc相比,我们的方法使用简单的金属线串扰树网络将采样的模拟电平转换为数字代码。在这里,采样的模拟信号通过输入金属线,该输入金属线以树状布局电容耦合到一系列金属线,树(叶子)边缘的耦合电压决定输出。分辨率取决于分支的数量。我们展示了通过该机制在16n技术节点上实现的2位和3位ADC。我们的研究结果表明,与CMOS相比,串扰adc可以节省大量功耗;在50M Hz采样频率下,2位和3位adc的功耗分别为43.51μW和96.74μW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel Analog to Digital Conversion Concept with Crosstalk Computing
Analog to Digital Converters (ADCs) is the core component of computing systems forming a link between the external stimuli and digital microprocessor operations. Current CMOS based fast ADCs are difficult to scale due to the reliance on transistor sizing and high voltage operations. They also suffer from high power consumption. In this paper, we introduce a novel ADC design which uses the deterministic signal interference between metal lines as a mechanism for signal conversion. In contrast to CMOS ADCs, our approach uses a simple crosstalk tree network of metal lines to convert sampled analog levels to digital code. Here, the sampled analog signal is passed through an input metal line which is capacitively coupled to a series of metal lines in a tree-like layout, and the coupled voltages on the edge of the tree (the leaves) determine the output. The resolution is dependent on the number of branches. We show 2-bit and 3-bit ADC implemented through this mechanism at 16n technology node. Our results indicate the possibility of huge power savings with Crosstalk ADCs in comparison to CMOS; for 2-bit and 3-bit ADCs the power consumption was found to be 43.51μW and 96.74μW respectively at 50M Hz sampling frequency.
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