Complementary Arranged Graphene Nanoribbon-based Boolean Gates

Yande Jiang, N. C. Laurenciu, S. Cotofana
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引用次数: 5

Abstract

With CMOS feature size heading towards atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanorib-bons (GNRs), owing to graphene’s excellent electronic properties, may serve as basic blocks for carbon-based nanoelectronics. In this paper we build upon the fact that GNR behaviour can be controlled according to some desired functionality via top/back gate contacts and propose to combine GNRs with complementary functionalities to construct Boolean gates. To this end, we introduce a generic GNR-based Boolean gate structure, composed of two GNRs, i.e., a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the inverted Boolean function. Subsequently, by properly adjusting GNRs’ dimensions and topology, we design 2-input AND, NAND, and XOR graphene-based Boolean gates, as well as 1-input gates, i.e., inverter and buffer. Our SPICE simulations indicate that the proposed gates exhibit a smaller propagation delay, from 23% for the XOR gate to 6× for the AND gate, and 2 orders of magnitude smaller power consumption, when compared with 7 nm CMOS based counterparts, while requiring a 1 to 2 orders of magnitude smaller active area footprint. These results clearly indicate that GNR-based gates have great potential as basic building blocks for future beyond CMOS energy effective nanoscale circuits.
互补排列石墨烯纳米带布尔门
随着CMOS特征尺寸向原子尺寸发展,不合理的静态功率、可靠性和经济影响正在加剧,促使人们研究新的材料、器件和/或计算范式。在这种情况下,石墨烯纳米棒(gnr)由于石墨烯优异的电子特性,可以作为碳基纳米电子学的基本块。在本文中,我们基于GNR行为可以通过顶/后门触点根据一些期望的功能进行控制的事实,并提出将GNR与互补功能结合起来构建布尔门。为此,我们引入了一种通用的基于GNR的布尔门结构,该结构由两个GNR组成,即执行门布尔函数的上拉GNR和执行倒布尔函数的下拉GNR。随后,通过适当调整gnr的尺寸和拓扑结构,我们设计了基于石墨烯的2输入与与、NAND和XOR的布尔门,以及1输入门,即逆变器和缓冲器。我们的SPICE模拟表明,与基于7纳米CMOS的对应物相比,所提出的门具有更小的传播延迟,从23%的异或门到6倍的与门,功耗小2个数量级,同时需要的有源面积占地面积小1到2个数量级。这些结果清楚地表明,基于gnr的栅极具有巨大的潜力,可以作为未来CMOS能量有效纳米级电路的基本构建模块。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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