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2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)最新文献

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Novel Manufacturing Process for Si Superjunction Power MOSFETs with Air-Gap and Insulating Cap Layer 具有气隙和绝缘帽层的硅超结功率mosfet的新制造工艺
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052133
Yuhki Fujino, Noboru Yokoyama, Takuya Yamaguchi, Hideki Okumura
{"title":"Novel Manufacturing Process for Si Superjunction Power MOSFETs with Air-Gap and Insulating Cap Layer","authors":"Yuhki Fujino, Noboru Yokoyama, Takuya Yamaguchi, Hideki Okumura","doi":"10.23919/eMDC/ISSM48219.2019.9052133","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052133","url":null,"abstract":"We target the problem of providing 5G network connectivity in rural zones by means of Base Stations (BSs) carried by Unmanned Aerial Vehicles (UAVs). Our goal is to schedule the UAVs missions to: i) limit the amount of energy consumed by each UAV, ii) ensure the coverage of selected zones over the territory, ii) decide where and when each UAV has to be recharged in a ground site, iii) deal with the amount of energy provided by Solar Panels (SPs) and batteries installed in each ground site. We then formulate the RURALPLAN optimization problem, a variant of the unsplittable multicommodity flow problem defined on a multiperiod graph. After detailing the objective function and the constraints, we solve RURALPLAN in a realistic scenario. Results show that RURALPLAN is able to outperform a solution ensuring coverage but not considering the energy management of the UAVs.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122431833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Identification Coding Rules and the Acceptance Criteria of Measuring Instruments 计量器具识别编码规则及验收准则
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/emdc/issm48219.2019.9052129
Chih-Jen Wang, Ya-chuan Chan
{"title":"The Identification Coding Rules and the Acceptance Criteria of Measuring Instruments","authors":"Chih-Jen Wang, Ya-chuan Chan","doi":"10.23919/emdc/issm48219.2019.9052129","DOIUrl":"https://doi.org/10.23919/emdc/issm48219.2019.9052129","url":null,"abstract":"Measuring instruments play a very important role in the semiconductor factory. They must be able to operate precisely and accurately; and instantly detect critical data including special characteristics and the full scale measurements of products, to help engineers detect and determine abnormalities. This is all to ensure the quality of products to reduce production costs, increase yield and create more benefits for the company.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127365039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Feature Extractions from a High-dimension Low-samples Data for Multi-dimension Virtual Metrology 多维虚拟计量的高维低样本数据特征提取
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052136
S. Arima, Huizhen Bu, Yuto Onuma, Kotaro Handa, Takuya Nagata
{"title":"Feature Extractions from a High-dimension Low-samples Data for Multi-dimension Virtual Metrology","authors":"S. Arima, Huizhen Bu, Yuto Onuma, Kotaro Handa, Takuya Nagata","doi":"10.23919/eMDC/ISSM48219.2019.9052136","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052136","url":null,"abstract":"This paper discussed the virtual metrology (VM) modelling of multi-dimensional multi classes to describe the relationship between the variables of a production machine's condition of and the estimated/forecasted product quality soon after finishing the machine processing. Combination of the Principle Component Analysis (PCA) and the LASSO (least absolute shrinkage and selection operator) technique of the sparse modelling were introduced to define the multi-dimensional quality. Because the high accuracy and quick computations are required for the VM modelling, in this study, the PCA-LASSO combination was applied before building the VM models based on the kernel SVM (kSVM), particularly the linear kernel for real-time use. Those usefulness was evaluated by three different data sets; a CVD (Chemical vapor deposition) process in an actual semiconductor factory, an open-data of higher dimension which is measured in a chemical process, and a scalable data which is generated by using a multivariate normal random numbers based on the original CVD data. We will investigate versatility of the proposed method.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126040725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimizing Chiller Switch-on Time Interval for Chiller Power Consumption Saving Via Big Data Analytics and Machine Learning Framework 通过大数据分析和机器学习框架优化冷水机开电间隔以节省冷水机功耗
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052110
Yu-Chu Tsai, C. Chien, Ying-Jen Chen, Meng-Ke Hsieh
{"title":"Optimizing Chiller Switch-on Time Interval for Chiller Power Consumption Saving Via Big Data Analytics and Machine Learning Framework","authors":"Yu-Chu Tsai, C. Chien, Ying-Jen Chen, Meng-Ke Hsieh","doi":"10.23919/eMDC/ISSM48219.2019.9052110","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052110","url":null,"abstract":"In semiconductor manufacturing, the chiller water system requires huge energy consumption, especially in the countries which have high temperature and humidity climate such as Taiwan. In order to minimize chiller power consumption without affecting the environment of wafer production, optimizing chiller system operations become a crucial issue. Conventionally, chiller operations greatly depend on engineers' practical experiences. However, various uncertainties, including changeable weather and complicated chiller combinations, lead to inconsistent decisions of switching chiller machines as well as energy waste [1]. To improve the operational performance of the system for energy saving, researchers have proposed many different types of solutions, but those technologies are not easy to widely adopted in practical applications due to the complicated and limited operations and models.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131096892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Tungsten Gate Replacement Process Optimization in 3D NAND Memory 3D NAND存储器中钨栅替换工艺优化
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052087
T. Luoh, YuKai Huang, Chimin Chen, Yung-tai Hung, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen
{"title":"Tungsten Gate Replacement Process Optimization in 3D NAND Memory","authors":"T. Luoh, YuKai Huang, Chimin Chen, Yung-tai Hung, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen","doi":"10.23919/eMDC/ISSM48219.2019.9052087","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052087","url":null,"abstract":"The impact of fluorine [F] amount generated from conventional WCVD process and ALD WCVD process on SONOS charge-trapping 3D NAND memory are investigated. The damage degree of blocking oxide is an index for fluorine penetration through TiN/Al2O3 then further impacts the voltage break down (VBD) of ONO device characteristics. As compared to conventional WCVD process, ALD WCVD process with laminar 2D sequential growth can provide much better fill-in performance at word line, less fluorine trap at grain boundaries, damage-free of blocking oxide, minimal stress, and low resistance replacement gate to 3D NAND Flash.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122866279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Chemical-mechanical polishing (CMP) process of STI and DTI- Ching-Yu Hsieh STI和DTI的化学机械抛光(CMP)工艺-谢清玉
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052083
Shih-Ping Lee, Tzu-Hsuan Tseng, Chih-Hao Chuang, Chien-Ying Chuang, Cheng-Hung Cheng, Hsin-Ying Tung, Pin-Chieh Huang, Chung-Tien Chou
{"title":"Chemical-mechanical polishing (CMP) process of STI and DTI- Ching-Yu Hsieh","authors":"Shih-Ping Lee, Tzu-Hsuan Tseng, Chih-Hao Chuang, Chien-Ying Chuang, Cheng-Hung Cheng, Hsin-Ying Tung, Pin-Chieh Huang, Chung-Tien Chou","doi":"10.23919/eMDC/ISSM48219.2019.9052083","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052083","url":null,"abstract":"We target the problem of providing 5G network connectivity in rural zones by means of Base Stations (BSs) carried by Unmanned Aerial Vehicles (UAVs). Our goal is to schedule the UAVs missions to: i) limit the amount of energy consumed by each UAV, ii) ensure the coverage of selected zones over the territory, ii) decide where and when each UAV has to be recharged in a ground site, iii) deal with the amount of energy provided by Solar Panels (SPs) and batteries installed in each ground site. We then formulate the RURALPLAN optimization problem, a variant of the unsplittable multicommodity flow problem defined on a multiperiod graph. After detailing the objective function and the constraints, we solve RURALPLAN in a realistic scenario. Results show that RURALPLAN is able to outperform a solution ensuring coverage but not considering the energy management of the UAVs.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132834457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Bipolar ZrO2-Based Resistive RAM with High Resolution Ratio under proposed method 提出了一种基于双极zro2的高分辨率阻性RAM
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052085
C. Chen, Chi-Yuan Ma, Yang Chenghan, Shih-Chieh Pu, Lai Han Chao
{"title":"A Bipolar ZrO2-Based Resistive RAM with High Resolution Ratio under proposed method","authors":"C. Chen, Chi-Yuan Ma, Yang Chenghan, Shih-Chieh Pu, Lai Han Chao","doi":"10.23919/eMDC/ISSM48219.2019.9052085","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052085","url":null,"abstract":"An RRAM (resistive random-access memory) of MIM(metal-insulator-metal) structure, which occupies an area as low as 16 m<sup>2</sup>, is proposed in this letter. The bipolar HfO<inf>2</inf>-based RRAM devices shows low to high ON/OFF ratio (low means ratio is around 1, high means ratio is around 3) under different current and voltage compliance algorithms during SET and RESET steps. With and without forming step is not relative with the I<inf>SET</inf>/I<inf>RESET</inf>ratio. Electrode area size (16-1225 m<sup>2</sup>) is not relative with the I<inf>SET</inf>/I<inf>RESET</inf> ratio. More importantly, RRAM device is compatible in LOGIC BEOL (back end of the line). In this study, we proposed a data resolution of I<inf>SET</inf>/I<inf>RESET</inf>ratio and operation margin enlargement in ZrO<inf>2</inf> Ox RAM. In current art definition, data resolution of I<inf>SET</inf>/I<inf>RESET</inf> ratio is in the_range of 2-3 orders and operation margin is 4 V (operation voltage is ± 2 V). Proposed algorithm could provide I<inf>SET</inf>/I<inf>RESET</inf> ratio of_data resolution in a range of 3–5 and operation margin of 8 V. After 100 turns of test of retention, ZrO2 ReRAM showed data resolution of I<inf>SET</inf>/I<inf>RESET</inf>ratio, which degraded to 1. New methodology of R<inf>HRS</inf>/R<inf>LRS</inf> ratio showed higher data resolution in range of 3–5 orders.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115832566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[Copyright notice] (版权)
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/emdc/issm48219.2019.9052082
{"title":"[Copyright notice]","authors":"","doi":"10.23919/emdc/issm48219.2019.9052082","DOIUrl":"https://doi.org/10.23919/emdc/issm48219.2019.9052082","url":null,"abstract":"","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129207887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimizing Production Performance Through Trace-Level Chamber Analysis 通过痕量级室分析优化生产性能
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052132
K. Gan, T. Ho, Joe Lee
{"title":"Optimizing Production Performance Through Trace-Level Chamber Analysis","authors":"K. Gan, T. Ho, Joe Lee","doi":"10.23919/eMDC/ISSM48219.2019.9052132","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052132","url":null,"abstract":"In semiconductor manufacturing, individual process chamber integrity needs to be maintained. This is achieved through regular chamber cleaning and process kit replacement. Chamber to chamber matching is also critical for process quality control. When chambers are performing the same task, they are expected to produce statistically similar output. The matching needs to be maintained through cleaning cycles and verified after each maintenance event.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Process Control Technique to Dramatically Reduce Voids in Phosphorus-Doped Poly-Silicon for Trench Field-Plate MOSFETs 大幅减少沟场极板mosfet中掺磷多晶硅空隙的工艺控制技术
2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2019-09-01 DOI: 10.23919/eMDC/ISSM48219.2019.9052086
Saya Shimomura, Hiroaki Kato, T. Shiraishi, Tetsuya Ohno, Toshifumi Nishiguchi, K. Miyashita, Kenya Kobayashi
{"title":"Process Control Technique to Dramatically Reduce Voids in Phosphorus-Doped Poly-Silicon for Trench Field-Plate MOSFETs","authors":"Saya Shimomura, Hiroaki Kato, T. Shiraishi, Tetsuya Ohno, Toshifumi Nishiguchi, K. Miyashita, Kenya Kobayashi","doi":"10.23919/eMDC/ISSM48219.2019.9052086","DOIUrl":"https://doi.org/10.23919/eMDC/ISSM48219.2019.9052086","url":null,"abstract":"Silicon power MOSFETs have been used for a wide variety of electronic devices in many application fields. In order to obtain high breakdown voltage and low on-resistance, trench field-plate (FP) MOSFETs have been continuously developed in recent years. It is necessary to design deep trench and thick field-plate oxide for higher breakdown voltage FP-MOSFETs [1]–[6]. In state-of-the-art FP-MOSFETs, as shown in Fig. 1, high cell density design has been developed for the purpose of getting low on-resistance. Fundamentally, it needs to shrink cell pitch, which consists of trench width and mesa width. Forming vertical trench is one method to realize narrow cell pitch. Voids are, however, generated in source field-plate polysilicon or gate poly-silicon in general [7]. If voids are gathered widely at the bottom of the source field-plate polysilicon (Fig. 1(a)), the effect of field-plate such as high breakdown voltage and good device characteristics cannot be obtained properly. Furthermore, if voids are formed at the bottom edge of the gate poly-silicon (Fig. 1(b)), effective gate bottom edge is underlapped with p-base. Thus, it is difficult to form the channel inversion layer at gate oxide interface. As a result, the on-resistance becomes increased. Therefore, suppressing void generation is one of the most significant process controls for trench FP-MOSFETs.","PeriodicalId":398770,"journal":{"name":"2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124517337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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